Lattice MachXO PLD控制开发方案

Lattice 公司的MachXO PLD是非易失的可以无限次重新配置的可编逻辑器件PLD），具有256-2280个查找表（LUT），73-271个I/O，多达27.6Kb sysMEM嵌入区块RAM，多达7.7Kb分布式RAM，可编程的sysIO™缓冲器支持LVCMOS 3.3/2.5/1.8/1.5/1.2,LVTTL.PV和LVDS，Bus-LVDS,LVPECL,RSDS,器件支持3.3V,2.5V,1.8V或1.2V电源，IEEE 1532兼容的在系统编程，主要用在各种终端市场包括消费类电子，汽车电子，通信，计算，工业和医疗。本文介绍了MachXO PLD系列的主要特性，MachXO PLD控制开发套件主要特性以及MachXO LCMXO2280C控制评估板方框图，电路图和材料清单（BOM）。

The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
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