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[原创] NXP S32R274汽车雷达参考设计方案

关键词:汽车电子 汽车雷达 S32R274

时间:2018-10-16 10:54:16       作者:NXP       来源:中电网

nxp公司的S32R274是用于汽车和工业雷达的32位多核微控制器系列,采用Power Architecture®核,两个独立的e200z7260进行通用计算.器件集成了高性能信号处理特性,支持专业的汽车RADAR应用.此外,器件还集成了高精度模拟特性,以增强和各种RADAR RF器件的接口功能.本文介绍了S32R274主要特性和框图,以及汽车雷达参考设计RDK-S32R274主要特性和电路图.

The S32R is a 32-bit heterogeneous multi-core microcontrollerfamily primarily intended for use in computationally intensiveautomotive RADAR applications. The device family incorporates Power Architecture®cores arranged as twoindependent e200z7260 for general computation and theS32R274 device also features an e200z420 core with an e200z419 checker core running in delayed lockstepconfiguration for safety-critical and housekeeping tasks. Thefamily integrates high-performance signal processing features designed to support sophisticated automotive RADARapplications, and the S32R274 also integrates high accuracyanalog features to further enhance it’s ability to interface witha wide range of RADAR RF devices.

The S32R family requires multiple external power supplies tooperate. The main cores internal logic requires a 1.25 V powersupply. This can be supplied from an external source or onsome devices this can alternatively be provided by an internalDC-DC regulator that requires a dedicated supply. 3.3 V isrequired for the general purpose I/O, flash memory, analog front-end, external communications interfaces, and on-chip SAR analog to digital converter.

S32R274主要特性:

• Safety core: Power Architecture? e200Z4 32-bit CPU with checker core
• 2 cycle delayed lockstep
• Harvard architecture with 64-bit bus for data and instructions
• Dual issue: up to two instructions per clock cycle
• 8 KB instruction cache and 4 KB data cache
• 64 KB data local memory
• with background load/store: backdoor access
• 0-wait state for all read and 32/64-bit write accesses
• Low number of wait states for backdoor accesses
• Support for decorated storage
• Variable Length Encoding (VLE) compliant for higher code density
• Single precision floating point operations
• Computation cores: Power Architecture? e200Z7 32-bit CPU
• Dual issue: up to two instructions per clock cycle
• Harvard architecture with 64-bit bus for data instructions
• 16 KB instruction cache and 16 KB data cache
• 64 KB data local memory
• with background load/store: backdoor access
• 0-wait state for all read and 32/64-bit write accesses
• Low number of wait states for backdoor accesses
• Support for decorated storage
• Using variable length encoding (VLE) for higher code density
• 4-way integer processing unit (SPE2)
• 2-way single-precision Floating Point Unit (EFPU2)
• 2 MB on-chip code flash (FMC flash) with ECC
• Three ports (one per CPU) shared between code and data flash with 4 × 256 bit buffer for code and data flash including prefetch functions
• Data flash is part of the code flash module
• Including 64 KB EEPROM emulation
• 1.5 MB on-chip SRAM with ECC
• Decorated memory controller to support atomic read-modify-write operations
• Single- and double-bit error visibility is supported
• Up to four ports (one per CPU and SPT) and up to 8 banks allow simultaneous
accesses from different masters to different banks
• RADAR processing
• Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
• Cross Timing Engine (CTE) for precise timing generation and triggering
• Waveform generation module (WGM) for chirp ramp generation
• 4x 12-bit ΣΔ-ADC with 10 MSps
• One DAC with 10 MSps
• MIPICSI2 interface to connect external ADCs
• Four data lanes, with up to 1 Gbps per lane and in total
• One clock lane
• Memory Protection
• Each core memory protection unit provides 24 entries
• Data and instruction bus system memory protection Unit (SMPU) with 16 regiondescriptors each
• Register protection
• Clock Generation
• 40 MHz external crystal (XOSC)
• 16 MHz Internal oscillator (IRCOSC)
• Dual system PLL with one frequency modulated phase-locked loop (FMPLL)
• Low-jitter PLL to ΣΔ-ADC and DAC clock generation
• Functional Safety
• Enables up to ASIL-D applications
• End to end ECC ensuring full protection of all data accesses throughout thesystem, from each of the systems masters through the crossbar and into thememories and peripherals
• FCCU for fault collection and fault handling
• MEMU for memory error management
• Safe eDMA controller
• User selectable Memory BIST (MBIST) can be enabled to run out of variousreset conditions or during runtime
• Self-Test Control Unit (STCU2)
• Error Injection Module (EIM)
• On-chip voltage monitoring
• Clock Monitor Unit (CMU) to support monitoring of critical clocks
• Security
• Cryptographic Security Engine (CSE2) enabling advanced security management
• Supports censorship and life-cycle management via Password and DeviceSecurity (PASS) module
• Diary control for tamper detection (TDM)
• Support Modules
• Global Interrupt controller (INTC) capable of routing interrupts to any CPU
• Semaphore unit to manage access to shared resources
• Two CRC computation units with four polynomials
• 32-channel eDMA controller with multiple transfer request sources usingDMAMUX
• Boot Assist Module (BAM) supports internal flash programming via a serial link(LIN / CAN)
• Timers
• Two Periodic Interval Timers (PIT) with 32-bit counter resolution
• Three System Timer Module (STM)
• Three Software Watchdog Timers (SWT)
• Two eTimer modules with 6 channels each
• One FlexPWM module for 12 PWM signals
• Communication Interfaces
• Two Serial Peripheral interface (SPI) module
• Two inter-IC communication interface (I2C) modules
• One LINFlexD module
• One dual-channel FlexRay module with 128 message buffers
• Three FlexCAN modules with configurable buffers
• CAN FD optionally supported on 2 FlexCAN modules
• One ENET MAC supporting MII/RMII/RGMII interface
• Supports 10/100 Mbps (MII/RMII/RGMII) and >100 Mbps (RGMII)
• Supports IEEE1588 timestamps and PTP
• Zipwire high-speed serial communication
• Supports LFAST and SIPI protocol
• Fast interprocessor communication with 320 Mbps gross data rate
• DMA based access to memory resources
• Debug Functionality
• 4-pin JTAG interface and Nexus/Aurora interface for serial high-speed tracing
• e200Z7 core and e200Z4 core: Nexus development interface (NDI) per IEEEISTO
5001-2012 Class 3+
• All platform bus masters except CSE can be monitored via Nexus/Aurora
• Device/board boundary Scan testing supported with per Joint Test Action Group(JTAG) (IEEE 1149.1) and 1149.7 (cJTAG)
• On-chip control for Nexus development interface by JTAGM module
• Two analog-to-digital converters (SAR ADC)
• Each ADC supports up to 16 input channels
• Cross Trigger Unit to enable synchronization of ADC conversions with eTimer
• On-chip voltage DC/DC regulator for core clock (VREG)
• Two Temperature Sensors (TSENS)

目标应用:

Automotive
Intelligent Roadside Unit

图1.S32R274框图

汽车雷达参考设计RDK-S32R274

Built in partnership with Colorado Engineering Inc., the RDK-S32R274 radar reference platform allowsrapid prototyping of high-performance radarapplications. The solution combines a robusthardware design and automotive-grade radarsoftware to enable customers to rapidly developproducts optimized to meet specific requirements.

Utilizing a modular architecture, the differentmodules in the RDK-S32R274 can be optimized tocreate a customizable development platform.

Developed to support high-performancecapabilities such as MIMO (Multiple input, multipleoutput), steerable beams and digital beamforming, this platform provides enough performance headroom for tasks such as radarcross section (RCS) measurements,target tracking,collision avoidance and occupancy sensing.

雷达参考设计RDK-S32R274主要特性:

An end-to-end NXP enabled solution featuring:
NXP S32R27 marketing leading Radar Processor
NXP TEF8102 RFCMOS Transceiver
NXP FS8410 Power Management IC
Automotive Hardware Design Methodologies
NXP Automotive-Grade software development kit
End-to-end Automotive Radar Reference Design Kit
Automotive-Grade Software Development Kit
Enables NCAP Applications (ACC & AEB)
Full Design Platform enables engineers to optimize application
Rapidly reduces customers time-to-market
Leverages market leading Performance/Watt Radar processor

雷达参考设计RDK-S32R274典型应用:

uAdaptive cruise control
uEmergency braking
uCollision avoidance
uOccupancy detection
uNXP S32R274 automotive radar microcontroller
uNXP TEF8102 77 GHz radar transceiver
uRobust antenna design enabling customer optimization
uMax range: 180 m with range accuracy: 0.175 m
uAngle resolution: 4.25° with angle accuracy; +/-0.25°
uApplication software provided using NXP automotivequalifiedradar software development kit (rSDK)
uAutomotive-grade hardware design

图2.雷达参考设计RDK-S32R274外形图

雷达参考设计RDK-S32R274包括:

RDK w/ enclosure
Quick start guide
Power cables
Ethernet cable

图3.雷达参考设计RDK-S32R274电路图(1)

图4.雷达参考设计RDK-S32R274电路图(2)

图5.雷达参考设计RDK-S32R274电路图(3)

图6.雷达参考设计RDK-S32R274电路图(4)

图7.雷达参考设计RDK-S32R274电路图(5)

图8.雷达参考设计RDK-S32R274电路图(6)

图9.雷达参考设计RDK-S32R274电路图(7)
详情请见:
https://www.nxp.com/docs/en/data-sheet/S32R274DS.pdf
https://www.nxp.com/downloads/en/schematics/SCH-28921.pdf
S32R274DS.pdf
SCH-28921.pdf

 

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