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[原创] NXP MPC5748G 32位160MHz MCU开发方案

关键词:Power Architecture MCU 汽车电子 网络通信

时间:2017-08-04 10:30:32       作者:NXP       来源:中电网

nxp公司的MPC5748G是采用2x160MHz Power Architecturee200Z4核32位MCU,是高度集成的安全的单片解决方案.具有增强的低功耗,增强性能和更有效的硬件安全模式,单精度浮点运算,8KB指令缓存和4KB数据缓存,可变长度编码(VLE)大大地改善了代码密度,主要用在中央车身控制模块,网关模块以及工业网络和控制应用.本文介绍了MPC5748G主要特性,框图,以及评估板MPC5748G-LCEVB主要特性和电路图.

The MPC574xB/C/G family of MCUs provides a highly integrated, safe and secure single-chip solution for next-generation central body control, gateway and industrial applications.Enhanced low-power capabilities provide increased functionality with more efficient operationHardware security module protects ECUs against various attack scenarios.

Functional safety support simplifies compliance for automotive safety systems targeting ISO 26262 and higher-end ASIL levelsComprehensive development tools simplify and accelerate system design Complimentary S32 Design studio IDE with automotive-grade Software Development Kit (SDK)Autosar MCAL and OS in a 3rd party ecosystemVarious Evaluation boards available to get started

MPC5748G主要特性:

• 2 x 160 MHz Power Architecture? e200Z4 Dual issue,32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant codedensity improvements
• 1 x 80 MHz Power Architecture? e200Z2 Single issue,32-bit CPU
– Using variable length encoding (VLE) forsignificant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores generate singleerror correction, double error detection (SECDED)code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 6 MB on-chip flash supported with the flashcontroller
– 3 x flash page buffers (3 port flash controller)
– 768 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• System Memory Protection Unit (SMPU) with up to 32region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routinginterrupts to any CPU
• Multiple crossbar switch architecture for concurrentaccess to peripherals, flash, and RAM from multiplebus masters
• 32-channels eDMA controller with multiple transferrequest sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flashprogramming via a serial link (LIN / SCI)
• Analog
– Two analog-to-digital converters (ADC),one 10-bitand one 12-bit
– Three analogue comparators
– Cross Trigger Unit to enable synchronization ofADC conversions with a timer event from theeMIOS or from the PIT
• Communication
– Four Deserial Peripheral Interface (DSPI)
– Six Serial Peripheral interface (SPI)
– 18 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (IIC)
– One USB OTG Controller (USB_0) and One USBSPH Controller (USB_1) with ULPI Interface.
– ENET complex (10/100 Ethernet) that supportsMulti queue with AVB support, 1588,and MII/RMII
– 2 x ENET with L2 switch
– Secure Digital Hardware Controller (uSDHC)
– Dual-channel FlexRay Controller
• Audio
– 3 x Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating inconjunction with the SAIs
• Configurable I/O domains supporting FLEXCAN,LINFlex, Ethernet, USB, MLB, uSDHC and generalI/O
• Supports wake-up from low power modes via theWKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200Z2core:NDI per IEEE-ISTO 5001-2008Class3+
– e200Z4 core(s): NDI per IEEE-ISTO 5001-2008Class 3+
• Timer
– 16 Periodic Interrupt Timers (PITs)
– Three System Timer Module (STM)
– Four Software WatchDog Timers (SWT)
– 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and1149.7 (cJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL compliance
• Multiple operating modes
– Includes enhanced low power operation

图1.MPC5748G框图

评估板MPC5748G-LCEVB

This user guide details the setup and configuration of the NXP MPC5748G Low Cost Evaluation Board (hereafter referred to as the LCEVB). The LCEVB is intended to provide a mechanism for easy evaluation of the MPC5748G family of microcontrollers, and to facilitate basic hardware and software development.

Note that the LCEVB has a limited feature set compared to the main MPC574xG customer EVB and is intended for evaluation purposes. Customers moving to serious development activities are recommended to purchase the fully functional customer EVB which also has device specific daughter cards.

The LCEVB is intended for bench / laboratory use and has been designed using normal temperature specified components (+70 ℃ ).

This product contains components that may be damaged by electrostatic discharge. Observe precautions for handling electrostatic sensitive devices when using the LCEVB.


图2.评估板MPC5748G-LCEVB外形图

评估板MPC5748G-LCEVB主要特性:

 Single 5 V DC external power supply input with on-board 3.3 V regulator. Power is supplied via a 2.1 mm barrel style power jack. 
 Simple jumper less configuration (enhanced configuration is possible via 0 Ohm Resistors and optional jumpers if required). 
 Master power switch and regulator status LED. 
 USB Serial interface.
 2 x High Speed CAN transceiver routed to 3-way headers. 
 2 x LIN interfaces routed to 3-way headers. 
 Main clock supplied from on board crystal. 
 User reset switch with reset status LED’s. 
 Ethernet PHY and RJ45 socket (configured for MII mode). 
 USB Type A Host interface. 
 2 x FlexRay interfaces with standard 2-pin connectors. 
 14-pin JTAG connector.
 4 user LED’s wired to MCU ports. 
 2 user pushbutton switches wired to MCU ports. 
 Hexadecimal encoded switch wired to 4 MCU ports. 
 Simple potentiometer connected to analogue input channel. 

图3.评估板MPC5748G-LCEVB功能框图

图4.评估板MPC5748G-LCEVB电路图(1)

图5.评估板MPC5748G-LCEVB电路图(2)

图6.评估板MPC5748G-LCEVB电路图(3)

图7.评估板MPC5748G-LCEVB电路图(4)

图8.评估板MPC5748G-LCEVB电路图(5)

图9.评估板MPC5748G-LCEVB电路图(6)

图10.评估板MPC5748G-LCEVB电路图(7)

图11.评估板MPC5748G-LCEVB电路图(8)

图12.评估板MPC5748G-LCEVB电路图(9)

图13.评估板MPC5748G-LCEVB电路图(10)

图14.评估板MPC5748G-LCEVB电路图(11)

图15.评估板MPC5748G-LCEVB电路图(12)

图16.评估板MPC5748G-LCEVB电路图(13)

图17.评估板MPC5748G-LCEVB电路图(14)

图18.评估板MPC5748G-LCEVB电路图(15)
详情请见:
http://www.nxp.com/docs/en/data-sheet/MPC5748G.pdf
http://www.nxp.com/docs/en/user-guide/MPC5748G-LCEVB_UG.pdf
以及http://www.nxp.com/downloads/en/schematics/MPC5748G-LCEVB-SCH.pdf
MPC5748G.pdf
MPC5748G-LCEVB-SCH.pdf
MPC5748G-LCEVB_UG.pdf

 

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