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NS ADC16V130高性能CMOS模数转换方案

关键词:通信技术 3G手机 NS ADC16V130

时间:2009-07-16 17:06:00       来源:NS

NS公司的ADC16V130是单片高性能CMOS模数转换器,取样速率高达130MSPS,能把输入模拟信号转换成16位数字信号. ADC16V130采用差分流水线架构,具有数字误差修正和取样保持电路,以及自动上电校准.采用双电源1.8V和3.0V工作,具有降功耗和睡眠模式,可广泛用在高IF取样接收器,多载波基站接收器, GSM/EDGE, CDMA2000, UMTS, LTE 与WiMax,测量和测试设备,通信基础设备,数据采集以及手提仪表.本文介绍了ADC16V130的主要特性,方框图以及采用ADC16V130的低IF接收器参考计SP16130CH4RB的主要特性和详细电路图.

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm LLP package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.



图1.ADC16V130方框图

主要特性:


Dual Supplies: 1.8V and 3.0V operation
On chip automatic calibration during power-up
Low power consumption
Multi-level multi-function pins for CLK/DF and PD
Power-down and sleep modes
On chip precision reference and sample-and-hold circuit
On chip low jitter duty-cycle stabilizer
Offset binary or 2s complement data format
Full data rate LVDS output port
64-pin LLP package (9x9x0.8, 0.5mm pin-pitch)
ADC16V130应用:
High IF Sampling Receivers
Multi-carrier Base Station Receivers
GSM/EDGE, CDMA2000, UMTS, LTE and WiMax
Test and Measurement Equipment
Communications Instrumentation
Data Acquisition
Portable Instrumentation
低IF 接收器参考计SP16130CH4RB
The SP16130CH4RB Reference Board demonstrates a low IF receiver subsystem application including an ADC16V130 analog-to-digital converter (ADC) and LMK04031B clock conditioner which provides digitization and clocking as used in wireless infrastructure systems.
This subsystem reference design provides single to differential conversion and lowpass filtering of the input signal with an optimized, double-balun network and high dynamic range digitization to parallel LVDS outputs using the ADC16V130.
The 125 MHz low-jitter, LVPECL clock signal for the ADC is generated by a LMK04031B clock conditioner which demonstrates less than 250 fs of total jitter over the input bandwidth of the ADC.
The measured system performance demonstrates a large signal SNR of 75.8 dBFS and SFDR greater than 84 dBFS for a -1 dBFS, 52 MHz input signal and a sampling frequency of 125 MSPS. For small signals, the performance improves to 78.0 dBFS SNR and greater than 94 dBFS SFDR.
Evaluation of this reference board is simplified with the WaveVision 5.1 Data Capture Board and WaveVision 5 software.

SP16130CH4RB主要特性:


Key Features of the SP16130CH4RB Low IF Receiver Reference Design Board
■Demonstrates a subsystem architecture used in wireless infrastructure systems and frequency domain analyzers
■Configured for input frequencies between 5 and 52 MHz
■Board comes fully assembled and tested
■Single (+5V) supply needed
■All ADC features can be exercised
■Featured Products Include:
—ADC16V130 16-bit, 130 Megasample per second (MSPS) ADC with parallel LVDS outputs
—LMK04031B low-jitter precision clock conditioner consisting of cascaded phase locked loops (PLLs), an internal voltage controlled oscillator (VCO) and a distribution stage
—Several energy-efficient power management ICs
■Large-signal (-1 dBFS) performance for a 52 MHz input signal:
—SNR = 75.8 dBFS
—SFDR > 84 dBFS
■Small-signal (-20 dBFS) performance for a 52 MHz input signal:
—SNR = 78.0 dBFS
—SFDR > 94 dBFS
■Total integrated jitter < 250 fs
■PIC Loader board included with reference board for quick and easy configuration of the LMK04031B
■Compatible with the WaveVision 5.1 Data Capture Board and WaveVision 5 software for simplified evaluation



图2.SP16130CH4RB参考设计外形图



图3.SP16130CH4RB电路图-ADC部分



图4.SP16130CH4RB电路图-LMK部分



图5.SP16130CH4RB电路图-电源部分


下表为SP16130CH4RB材料清单(BOM):



详情请见:
http://www.national.com/ds/DC/ADC16V130.pdf


http://webench.national.com/rd/RD/RD-170.pdf

 

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