Renesas RC32504A新一代FemtoClock 2频率合成器解决方案

Renesas公司的RC32504A是先进的高性能新一代FemtoClock 2频率合成器,采用简单的低成本基频模式石英晶体作为低频参考,用来合成相位噪声低于 0.5 ps RMS,频率高达 1.3 GHz 的高品质时钟信号,还具有抖动衰减模式,在接收噪声参考时,也能提供100fs 的输出抖动性能.FemtoClock器件是能够生成参考频率的完全可定制独立解决方案,可用于代替高性能应用中的晶体和SAW振荡器.与固定频率振荡器不同,FemtoClocks采用频率合成技术(时钟合成器),可提供多个时钟频率,而且在任何应用中都具有更高的灵活性.器件的抖动低至64fs(典型值)RMS,具有600mW低功耗.采用24和28引脚4mm x 4mm QFN封装,具有四个差分输出的单,双输入选项.电源噪声抑制优于-80dB,输出到输出隔离为-80dBc.符合ITU-T G.8262和G.8262.1标准.支持高达1MHz I2C或高达20MHzSPI串行处理器端口.主要用于增强型同步以太网/OTN以及可编FiberOptic模块的基准时钟.本文介绍了RC22504A主要特性,框图和详细框图以及评估板RC32504A /RC22504A EVB主要特性,框图,功能分布图,以及电路图和材料清单.

The RC22504A is a small, low-power timingcomponent designed to be placed immediatelyadjacent to a PHY, switch, ASIC or FPGA thatrequires several reference clocks with jitterperformance less than 100fs (max). The RC22504Acan act as a frequency synthesizer to locally generatethe reference clock or as a DCO for frequency

margining or OTN clock applications.

The device is a member of Renesas highperformanceFemtoClock2 family.

RC22504A主要特性:

• Jitter as low as 64 fs RMS maximum (10Hz to20MHz)

• PLL core consists of fractional-feedback AnalogPLL (APLL)

○ Operates from a 25MHz to 80MHz crystal or XO

○ APLL frequency independent of input / crystalfrequency

○ Operates as a frequency synthesizer or DigitallyControlled Oscillator (DCO)

○ DCO has tuning granularity of < 1ppb

• Programmable status output

• 4 differential / 8 LVCMOS outputs

○ Any frequency from 10MHz to 1GHz (180MHz forLVCMOS)

○ Programmable output buffer supports HCSL(DC-coupled), LVDS/LVPECL/CML (AC-c...