[原创] Lattice ECP5和ECP5－5G FPGA系列VIP处理器解决方案

Lattice公司的ECP5/ECP5-5G FPGA系列提供了高性能特性如增强DSP架构,高速SERDES和高速源同步接口,采用40nm技术,使得器件非常适合于量大高速和低成本的应用.器件的查找表(LUT)高达48K逻辑单元,支持多达365个用户I/O,提供多达156个18x18乘法器和各种并行I/O标准,采用可配置SRAM逻辑技术,提供基于LUT的逻辑,分布式和嵌入式存储器,锁相环(PLL),延迟锁定环(DLL),支持预制源同步I/O,增强sysDSP slices和高挡配置,包括加密和双引导功能.本文介绍了ECP5和ECP5-5G FPGA系列主要特性,LFE5UM/LFE5UM5G-85器件简化框图以及ECP5 VIP 处理器板主要特性,框图,电路图和材料清单.

The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, high-speed, and low-cost applications.

The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/Os. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards.
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