[原创] TI多路JESD204B兼容15GHz时钟参考设计TIDA－01021

TI公司的TIDA-01021是用于DSO,雷达和5G无线测试仪的多路JESD204B兼容15GHz时钟参考设计,可产生10MHz到15GHz时钟和用于JESD204B接班口的SYSRE,15GHz时的1KHz失调相位噪音小于–104 dBc/Hz,采用ADC12DJ3200高速转换器评估板EVM可使板-板时钟偏移小于10ps,5.25GHz输入信号时的SNR为49.6dB,主要用在高性能示波器,相阵列雷达,无线通信测试仪和直接取样软件定义无线电.本文介绍了参考设计TIDA-01021主要特性和系统指标,多种性能测量建立图,以及电路图,材料清单和PCB设计图.

Multichannel JESD204B 15-GHz Clocking ReferenceDesign for DSO, Radar, and 5G Wireless Testers.The TIDA-01021 design is capable of supporting twohigh-speed channels on separate boards by using TI’sLMX2594 wideband PLL with integrated VCOs togenerate a 10-MHz to 15-GHz clock and SYSREF forJESD204B interfaces. The 10-kHz offset phase noiseis < –104 dBc/Hz for a 15-GHz clock frequency. ThisTI Design uses TI ’s ADC12DJ3200 high-speedconverter EVMs to achieve a board-to-board clock skew of < 10 ps and an SNR of 49.6 dB with a 5.25-GHz input signal. All key design theories aredescribed, guiding users through the part selectionprocess and design optimization. Finally, this referencedesign presents schematics, board layout, hardware testing, and results.
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