Altera Arria II GX FPGA开发方案

本文介绍了Arria II GX FPGA亮点，高速收发器特性，Arria II GX FPGA架构以及Arria II GX FPGA 开发套件主要特性，开发板方框图，详细的开发板电路图和材料清单（BOM）。

Arria II FPGAs: Cost-Optimized, Lowest Power 6G Transceiver FPGAs

The Arria® II GX device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express® (PIPE) (PCIe®), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus® II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera®. The Arria II GX device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy.

Arria II GX FPGA亮点：

The Arria II GX device features consist of the following highlights:

■ 40-nm, low-power FPGA engine

■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■ Eight-input fracturable look-up table (LUT)

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