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[原创] TI DRA74P多核SoC处理器汽车应用方案

关键词:ARM Cortex-A15 MCU SoC处理器 汽车电子

时间:2019-11-15 11:16:32       来源:中电网

TI公司的DRA74xP和DRA75xP是多核SoC汽车应用处理器,能满足汽车现代数字驾驶座体验的密集处理需求.该器件能使原始设备制造商(OEM)和原始设计制造商(ODM)更快地实现创新的连接技术,语音识别和音频流等. Jacinto 6 Plus器件(DRA74xP和DRA75xP)通过最大灵活性的全集成混合处理器解决方案实现高处理性能,同时还结合了有高度集成的外设集的可编程的视频处理.可编程是由双核Arm Cortex-A15 RISC CPU和Neon™延伸,TI C66x VLIW浮点DSP核, Vision AccelerationPac来提供.ARM允许开发人员单独对DSP和协处理器的算法编程保持控制功能,因此降低了系统软件复杂性.器件的架构设计用于信息娱乐应用,支持视频,图像和图形处理:全高清视频(1920×1080p,60 fps),多种视频输入和视频输出,2D和3D图像;器件还具有双路Arm® Cortex®-A15微处理器子系统,高达两个C66x浮点VLIW DSP,目标代码完全和C67x 与C64x+兼容,多达32个16x16位定点乘法/周期,集成多达2.5MB L3 RAM以及L3和L4互连.主要用在人机接口(HMI),导航,数字和模拟无线电,后排信息娱乐,多媒体播放器,网页浏览,ADAS集成,汽车数字驾驶座体验以及信息娱乐/中控面板.本文介绍了DRA74xP和DRA75xP主要特性,框图以及32位和16位DDR2高级电路图,DRA77xP/DRA76xP-ACD CPU EVM 板主要特性,电源分布框图和DRA77xP/DRA76xP-ACD CPU EVM 板材料清单.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intensEPROcessing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers(ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming,and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of afully integrated mixed processor solution. The devices also combine programmable video processing witha highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66xVLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allowsdevelopers to keep control functions separate from other algorithms programmed on the DSP andcoprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, includingsupport for secure boot, debug security and support for trusted execution environment are available onHigh-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100standard.

DRA74xP和DRA75xP主要特性:

• Architecture Designed for InfotainmentApplications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
– 2D and 3D Graphics
• Dual Arm® Cortex®-A15 MicroprocessorSubsystem
• Up to Two C66x Floating-Point VLIW DSP
– Fully Object-Code Compatible with C67x andC64x+
– Up to Thirty-Two 16 x 16-Bit Fixed-PointMultiplies per Cycle
• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• Two DDR2/DDR3/DDR3L Memory Interface(EMIF) Modules
– Supports up to DDR2-800 and DDR3-1333
– Up to 2GB Supported per EMIF
• Dual ARM® Cortex®-M4 Image Processing Units(IPU)
• Up to Two Embedded Vision Engines (EVEs)
• Imaging Subsystem (ISS)
– Image Signal Processor (ISP)
– Wide Dynamic Range and Lens DistortionCorrection (WDR and Mesh LDC)
– One Camera Adaptation Layer (CAL_B)
• IVA Subsystem
• Display Subsystem
– Display Controller with DMA Engine and up toThree Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0Compliant
• Video Processing Engine (VPE)
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante® GC320 Core
• Dual-Core PowerVR® SGX544 3D GPU
• Two Video Input Port (VIP) Modules
– Support for up to Eight Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)Controller
• 2-Port Gigabit Ethernet (GMAC)
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Five Inter-Integrated Circuit (I2C) Ports
• HDQ™/ 1-Wire® Interface
• SATA Interface
• Media Local Bus (MLB) Subsystem
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces(McSPI)
• Quad SPI (QSPI)
• Eight Multichannel Audio Serial Port (McASP)Modules
• SuperSpeed USB 3.0 Dual-Role Device
• Three High-Speed USB 2.0 Dual-Role Devices
• Four MultiMedia Card/Secure Digital/Secure DigitalInput Output Interfaces ( MMC™/ SD®/SDIO)
• PCI Express® 3.0 Subsystems with Two 5-GbpsLanes
– One 2-Lane Gen2-Compliant Port
– or Two 1-Lane Gen2-Compliant Ports
• Up to Two Controller Area Network (DCAN)Modules
– CAN 2.0B Protocol
• Modular Controller Area Network (MCAN) Module
– CAN 2.0B Protocol with Available FD (FlexibleData Rate) Functionality
• Up to 247 General-Purpose I/O (GPIO) Pins
• Real-Time Clock Subsystem (RTCSS)
• Device Security Features
– Hardware Crypto Accelerators and DMA
– Firewalls
– JTAG® Lock
– Secure Keys
– Secure ROM and Boot
– Customer Programmable Keys and OTP Data
• Power, Reset, and Clock Management
• On-Chip Debug with CTools Technology
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA(ABZ)

DRA74xP和DRA75xP应用:

• Human-Machine Interface (HMI)
• Navigation
• Digital and Analog Radio
• Rear Seat Entertainment
• Multimedia Playback
• Web Browsing
• ADAS Integration
• Integrated Automotive Digital Cockpit
• Infotainment / Center Stack

图1. DRA74xP和DRA75xP框图

图2.32位DDR2高级电路图

图3.16位DDR2高级电路图


图4.采用两个16位DDR3器件的32位一组DDR3接口电路

图5.采用四个8位DDR3器件的32位一组DDR3接口电路图

DRA77xP/DRA76xP-ACD CPU EVM 板

This user’s guide is intended for software and hardware engineers developing applications for the Jacinto6 high performance, multimedia application processor based on enhanced OMAP™ architectureimplemented with 28-nm technology. It describes the evaluation module (EVM) CPU board’s hardware,firmware and software functions supplied by Texas Instruments Inc.

The CPU board contains the (Jacinto 6 Plus/TDA2Px) applications processor, a companion PowerManagement ICs (TPS65917 + LP87565), Audio Codec (TLV320AIC3106), DDR3 DRAM, four differentFlash memories (QSPI, enhanced MultiMedia Card (eMMC), NAND and NOR), a multitude of interfaceports and expansion connectors. The board provides additional support components that provide softwaredebugging, signal routing and configuration controls that would not be needed in a final product.

Different version CPU boards will be built to support the development processes that include:
• Socketed processor used for wakeup, early software development, quick and easy chip revisionevaluation
• Soldered-down processor used for high performance Use Cases and evaluations

图6. DRA77xP/DRA76xP-ACD CPU EVM 板外形图

Jacinto DRA7xP评估模块(EVM577PBG-01-00-00)

CPU板主要特性:
• Processor:
– DRA77xP/DRA76xP/TDA2Px (Superset SoC) (23 mm x 23 mm package, 0.8 mm pitch)
– Support for corresponding socket
• Power supply:
– 12 V DC input
– Optimized power management solution
– Compliant with SoC power sequencing requirements
– Integrated power measurement
• PCB:
– Dimension (W x D) 220mm x 170mm
– 100% PTH technology
• Memory:
– DRAM (DDR3L-1333): 4 Gbyte (2 GByte for each EMIF) (EMIF1 optionally supports ECC)
– Quad Serial Peripheral Interface (SPI) Flash: 256 M-bit
– eMMC Flash: 8G-bit (v4.51 compliant)
– NAND Flash: 4G-bit
– NOR Flash: 512 M-bit
– Serial EEPROM, 32K-bit
– MicroSD Card Cage
• Boot mode selection DIP switch
• Digital Temperature Sensor (TMP102)
• JTAG/Emulator:
– 60 pin MIPI Connector/Trace Connector
– Adapter for 20 pin-CTI adapter: 10 x 2, 1.27mm pitch
• Supported Interfaces and Peripherals:
– CAN Interface, two 2-wire PHY (either can also support CAN-FD)
– 2x USB Host receptacles (1x USB3.0 (micro-USB), 1x USB2.0 (Type-A))
– Audio Codec (AIC3106) with Headphone OUT, Line OUT, Line IN, Microphone IN
– 3x Video outputs (HDMI, RGB/LCD, FPD-Link III)
– Camera Sensor(s) supported via Leopard Imaging Module Interfaces (Parallel and MIPI)
– PCI Express (PCIe), 2x Channel
– SATA
– MLB and MLBP on Mictor connector
– Universal Asynchronous Receiver/Transmitter (UART) terminal via USB FTDI converter (mini-A/BUSB)
– COM8Q module interface for Bluetooth and WLAN support
– 2x RJ45 Gbit Ethernet (DP83867)
– I2C General-Purpose Input/Output (GPIO) Expander
• Expansion connectors to support application specific add-on boards

图7.CPU板正面图

图8.CPU板背面图

图9.CPU板框图

图10.电源分布框图
DRA77xP/DRA76xP-ACD CPU EVM 板材料清单见:
SPRR315_DRA76xP_DRA77xP_TDA2Px_ACD CPU Board BOM Rev C.xls
SPRR320_DRA76xP_DRA77xP_TDA2Px_ACD HDMI DISPLAY ADAPTER Board BOM Rev B.xls
详情请见;
http://www.ti.com/lit/ds/symlink/dra74p.pdf
http://www.ti.com/lit/ug/spruii5a/spruii5a.pdf
spruii5a.pdf
dra74p.pdf

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