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[原创] Silicon Lab Si5348网络同步时钟开发方案

关键词:以太网 网络通信 PLL 网络同步时钟

时间:2019-09-12 11:06:32       来源:中电网

Silicon Lab公司的Si5348是网络同步时钟器,用于SyncE/ 1588 PTP电信边界(T-BC)和从(T-SC)时钟,提供三个DSPLL.能通过串行接口单独配置和控制.每个DSPLL支持锁住,自由运行,以及具有选择DCO模式的运营滞留模式,以用于IEEE 1588应用.器件需要外接晶振和外接基准(TCXO或OCXO)来运行.基准输入(REF/REFb)确定了自由运行和滞留模式的频率精确度和稳定性.时钟的超低抖动为95fs,增强无障碍切换最小化输出相位瞬变,输入频率范围:外接晶体48-54MHz,REF时钟5-250MHz,差分时钟8kHz到750MHz,LVCMOS时钟:8 kHz 到250 MHz;输出频率范围:差分1 PPS 到 718.5 MHz, LVCMOS 1 PPS到 250 MHz.器件满足以下规范:ITU-T G.8262 (SyncE) EEC Options 1and 2, ITU-T G.812 Type III, IV, ITU-T G.813 Option 1和Telcordia GR-1244, GR-253(Stratum-3/3E).主要用在同步以太网(SyncE)ITU-T G.8262 EEC Option 1 & 2,由ITU-T G.8273.2所定义的电信边界时钟(T-BC),IEEE 1588 (PTP)从时钟同步化,以及Stratum 3/3E, G.812, G.813网络同步.本文介绍了Si5348主要特性,框图和Si5348-E详细框图,以及开发板Si5348-E-EVB主要特性,功能框图,应用框图和电路图,材料清单和PCB设计图.

The Si5348 offers three DSPLLs that can be independently configured and controlled through the serial interface. Each of the DSPLLssupport locked, free-run, and holdover modes of operation with an optional DCO mode for IEEE 1588 applications. The device requiresan external crystal and an external reference (TCXO or OCXO) to operate. The reference input (REF/REFb) determines the frequencyaccuracy and stability while in free-run and holdover modes. The external crystal completes the internal oscillator circuit (OSC) which isused by the DSPLL for intrinsic jitter performance. There are three main inputs (IN0 - IN2) for synchronizing the DSPLLs. Input selectioncan be manual or automatically controlled using an internal state machine. Two additional manually selected inputs are available toDSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any of the DSPLLs using a flexible crosspoint connection.

Output 6 is the only output that can be configured for a 1 Hz output to support 1 PPS. The Si5348 combines the industry’s smallest footprint and lowest power network synchronizerclock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization.

The three independent DSPLLs™ are individually configurable as a SyncE PLL, IEEE 1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digitally controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588 (PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/OCXO reference input to determine the device’s frequency accuracy and stability.

The Si5348 is programmable via a serial interface with in-circuit programmable non-volatile memory so it always powers up into a known configuration. Programming the Si5348 is easy with ClockBuilder Pro™ software. Factory pre-programmed devices are also available.

Si5348主要特性:

• Three independent DSPLLs in a singlemonolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
• Ultra-low jitter of 95 fs
• Enhanced hitless switching minimizesoutput phase transients
• Input frequency range:
• External crystal: 48 to 54 MHz
• REF clock: 5 to 250 MHz
• Diff clock: 8 kHz to 750 MHz
• LVCMOS clock: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 1 PPS to 718.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Meets the requirements of:
• ITU-T G.8262 (SyncE) EEC Options 1and 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253(Stratum-3/3E)

Si5348应用:

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization

图1.Si5348框图

图2.Si5348-E详细框图

Si5348特性如下:

• Three independent DSPLLs in a single monolithic IC supportingflexible SyncE/IEEE 1588 and SETS architectures
• Ultra-Low Jitter
• 95 fs typ (12 kHz to 20 MHz)
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 & 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any inputfrequency
• Input frequency range:
• External crystal: 48–54 MHz
• REF clock: 5–250 MHz
• Diff clock: 8 kHz–750 MHz
• LVCMOS clock: 8 kHz–250 MHz
• Output frequency range:
• Differential: 1 PPS to 718.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Independent Frequency-on-the-fly for each DSPLL
• Enhanced hitless switching minimizes output phase transientsfor 8 kHz, 19.44 MHz, 25 MHz, and all other input frequencies.
• Pin or software controllable DCO on each DSPLL with typicalresolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/holdoveraccuracy and stability
• Programmable jitter attenuation bandwidth per DSPLL: 0.001Hz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,HCSL, CML
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring: LOS, OOF, LOL
• Serial Interface: I2C or SPI (3-wire or 4-wire)
• ClockBuilder Pro software simplifies device configuration
• 5 input, 7 output, 64 QFN
• Temperature range: –40 to +85℃

• Pb-free, RoHS-6 compliantSi5348 Rev E Data Sheet

图3.Si5348应用电路图:电信边界时钟

Si5348网络同步时钟开发板Si5348-E-EVB

Si5348网络同步时钟开发板Si5348-E-EVB包括:

Seamless download from ClockBuilder Pro to EVB
SMA connectors for high quality measurements
No external clocks are required for free-run evaluation
Real-time power and junction temperature measurements
Access all registers, LED indicators and I/O
Most configurations can be powered by USB

The Si5348-E-EVB is used for evaluating the Si5348 Network Synchronizer Clock for SyncE/1588 and Stratum 3/3E applications. The device revision is distinguished by a white 1 inch x 0.187 inch label with the text “SI5348-E-EB”in the lower left-hand corner of the board.(For ordering purposes only, the terms“EB” and “EVB”refer to the board and the kit respectively. In this document, the terms are synonymous in context.) The Si5348 contains three independent DSPLLs in a single IC with programmable jitter attenuation bandwidth on a per DSPLL basis. The Si5348-E-EVB supports three independentdifferential input clocks, two independent CMOS input clocks, and seven independentoutput clocks via onboard SMA connectors. The Si5348-E-EVB can be controlledand configured via a USB connection to a host PC running Silicon Labs’next generation Clock Builder Pro™ (CBPro™) software tool. Test points are provided onboard for external monitoring of supply voltages.

The device revision is distinguished by a white 1 inch x 0.187 inch label with the text “SI5348-E-EB” installed in the lower left hand corner of the board. (For ordering purposes only, the terms “EB” and “EVB” refer to the board and the kit respectively. For the purpose of this document, the terms are synonymous in context.

This kit comes with an OCXO board SiOCXO1-EB as well as a TCXO board SiTCXO1-EB. The OCXO or the TCXO are used on the reference input (REF) of the Si5348 to evaluate the holdover stability of the network synchronizer clock. Both boards are not needed at the same time, but they are both included in the kit to provide a comparison of the resulting performance.

开发板Si5348-E-EVB主要特性:

• Powered from USB port or external +5 Vpower supply via screw terminals
• Included SiOCXO1-EB reference OCXOboard allows for evaluation in standalone
and holdover mode.
• Included SiTCXO1-EB reference TCXOboard allows for evaluation in standalone
and holdover mode.
• CBPro™ GUI programmable VDD supplyallows device supply voltages from 3.3,
2.5, or 1.8 V
• CBPro™ GUI programmable VDDOsupplies allow each of the seven outputsto have its own supply voltage selectablefrom 3.3, 2.5, or 1.8 V
• CBPro™ GUI allows control andmeasurement of voltage, current, andpower of VDD and all 8 VDDO supplies
• Status LEDs for power supplies andcontrol/status signals of Si5348
• SMA connectors for input clocks, outputclocks and optional external timingreference clock

图4.开发板Si5348-E-EVB外形图

图5.SiOCX01-EB(左) SiTCX01-EB(右)

图5.开发板Si5348-E-EVB功能框图

图6. 开发板Si5348-E-EVB电路图(1)

图7. 开发板Si5348-E-EVB电路图(2)

图8. 开发板Si5348-E-EVB电路图(3)

图9. 开发板Si5348-E-EVB电路图(4)

图10. 开发板Si5348-E-EVB电路图(5)

图11. 开发板Si5348-E-EVB电路图(6)

图12. 开发板Si5348-E-EVB电路图(7)

图13. 开发板Si5348-E-EVB电路图(8)

图14. 开发板Si5348-E-EVB电路图(9)

图15. 开发板Si5348-E-EVB电路图(10)

图16. 开发板Si5348-E-EVB电路图(11)

图17. 开发板Si5348-E-EVB电路图(12)

图18. 开发板Si5348-E-EVB电路图(13)

图19. 开发板Si5348-E-EVB电路图(14)

图20. 开发板Si5348-E-EVB电路图(15)

图21. 开发板Si5348-E-EVB电路图(16)

图22. 开发板Si5348-E-EVB电路图(17)

图23. 开发板Si5348-E-EVB电路图(18)

图24. 开发板Si5348-E-EVB电路图(19)

图25. 开发板Si5348-E-EVB电路图(20)

图26. 开发板Si5348-E-EVB电路图(21)

图27. 开发板Si5348-E-EVB电路图(22)

图28. 开发板Si5348-E-EVB电路图(23)

图29. 开发板Si5348-E-EVB电路图(24)

图30. 开发板Si5348-E-EVB电路图(25)

图31. 开发板Si5348-E-EVB电路图(26)

图32. 开发板Si5348-E-EVB电路图(27)

图33. 开发板Si5348-E-EVB电路图(28)

图34. 开发板Si5348-E-EVB电路图(29)

图35. 开发板Si5348-E-EVB电路图(30)

图36. 开发板Si5348-E-EVB电路图(31)

图37. 开发板Si5348-E-EVB电路图(32)

图38. 开发板Si5348-E-EVB电路图(33)

图39. 开发板Si5348-E-EVB电路图(34)

图40. 开发板Si5348-E-EVB电路图(35)

图41. 开发板Si5348-E-EVB电路图(36)

图42. 开发板Si5348-E-EVB电路图(37)

图43. 开发板Si5348-E-EVB电路图(38)

图44. 开发板Si5348-E-EVB电路图(39)

图45. 开发板Si5348-E-EVB电路图(40)

图46. 开发板Si5348-E-EVB电路图(41)

图47. 开发板Si5348-E-EVB电路图(42)

图48. 开发板Si5348-E-EVB电路图(43)
开发板Si5348-E-EVB材料清单:







图49. 开发板Si5348-E-EVB PCB设计图(1)

图50. 开发板Si5348-E-EVB PCB设计图(2)

图51. 开发板Si5348-E-EVB PCB设计图(3)

图52. 开发板Si5348-E-EVB PCB设计图(4)

图53. 开发板Si5348-E-EVB PCB设计图(5)

图54. 开发板Si5348-E-EVB PCB设计图(6)

图55. 开发板Si5348-E-EVB PCB设计图(7)

图56. 开发板Si5348-E-EVB PCB设计图(8)

图57. 开发板Si5348-E-EVB PCB设计图(9)

图58. 开发板Si5348-E-EVB PCB设计图(10)

图59. 开发板Si5348-E-EVB PCB设计图(11)

图60. 开发板Si5348-E-EVB PCB设计图(12)

图61. 开发板Si5348-E-EVB PCB设计图(13)

图62. 开发板Si5348-E-EVB PCB设计图(14)

图63. 开发板Si5348-E-EVB PCB设计图(15)

图64. 开发板Si5348-E-EVB PCB设计图(16)

图65. 开发板Si5348-E-EVB PCB设计图(17)

图66. 开发板Si5348-E-EVB PCB设计图(18)

图67. 开发板Si5348-E-EVB PCB设计图(19)

图68. 开发板Si5348-E-EVB PCB设计图(20)

图69. 开发板Si5348-E-EVB PCB设计图(21)

图70. 开发板Si5348-E-EVB PCB设计图(22)

图71. 开发板Si5348-E-EVB PCB设计图(23)

图72. 开发板Si5348-E-EVB PCB设计图(24)

图73. 开发板Si5348-E-EVB PCB设计图(25)

图74. 开发板Si5348-E-EVB PCB设计图(26)
详情请见:
https://www.silabs.com/documents/public/data-sheets/si5348-e-datasheet.pdf
https://www.silabs.com/documents/public/user-guides/ug362-si5348-e-evb.pdf
si5348-e-datasheet.pdf
ug362-si5348-e-evb.pdf
si5348-symbols.zip.zip

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