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[原创] Silicon Lab Si5395 12路超低抖动时钟倍频器解决方案

关键词:工业控制 测试测量 以太网 医疗图像

时间:2019-08-26 11:40:39       来源:中电网

Silicon Lab公司的Si5395/94/92抖动衰减器组合了第四代DSPLL™和Multi-Synth™技术,提供了超低抖动(69fs),可用于高性能的应用如56G SerDes.所有的PLL元件集成在单片上,从而消除和分立解决方案有关的噪音耦合问题.器件级别J/K/L/M/E集成了基准以节省板的空间,提高系统可靠性,降低由温度梯度所引起的声发射噪声效应,而级别A/B/C/D/P则采用外接晶体(XTAL)或晶体振荡器(XO)基准.级别P的抖动为69fs RMS,级别E的抖动为71fs RMS.输入频率范围,差分为8 kHz 到 750 MHz, LVCMOS为8 kHz 到 250 MHz;而输出频率范围,差分为100Hz 到 1028 MHz, LVCMOS为100Hz 到 250 MHz.器件满足G.8262, E.8262.1 EEC标准.主要用在56G/112G PAM4 SerDes时钟,OTN多发探测仪和转发器, 10/40/100/200/400G网络线路卡, 10/40/100/400 GbE同步以太网(ITU-T G.8262),医疗图像和测试测量.本文介绍了Si5395/94/92主要特性,简化框图和框图,典型56G SerDes应用电路和同步线路卡SyncE电路图以及评估板Si5394 EVB主要特性,功能框图和电路图与材料清单.

The Si5395/94/92 Jitter attenuators combine fourth-generation DSPLL™ and Multi-Synth™ technologies to deliver ultra-low jitter (69 fs) for high performance applications like 56G SerDes. They are used in applications that demand the highest levelof integration and jitter performance. All PLL components are integrated on-chip,eliminating the risk of noise coupling associated with discrete solutions. Devicegrades J/K/L/M/E have an integrated reference to save board space, improve systemreliability and reduces the effect of acoustic emissions noise caused by temperatureramps..

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