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[原创] Silicon Lab Si5395 12路超低抖动时钟倍频器解决方案

关键词:工业控制 测试测量 以太网 医疗图像

时间:2019-08-26 11:40:39       来源:中电网

Silicon Lab公司的Si5395/94/92抖动衰减器组合了第四代DSPLL™和Multi-Synth™技术,提供了超低抖动(69fs),可用于高性能的应用如56G SerDes.所有的PLL元件集成在单片上,从而消除和分立解决方案有关的噪音耦合问题.器件级别J/K/L/M/E集成了基准以节省板的空间,提高系统可靠性,降低由温度梯度所引起的声发射噪声效应,而级别A/B/C/D/P则采用外接晶体(XTAL)或晶体振荡器(XO)基准.级别P的抖动为69fs RMS,级别E的抖动为71fs RMS.输入频率范围,差分为8 kHz 到 750 MHz, LVCMOS为8 kHz 到 250 MHz;而输出频率范围,差分为100Hz 到 1028 MHz, LVCMOS为100Hz 到 250 MHz.器件满足G.8262, E.8262.1 EEC标准.主要用在56G/112G PAM4 SerDes时钟,OTN多发探测仪和转发器, 10/40/100/200/400G网络线路卡, 10/40/100/400 GbE同步以太网(ITU-T G.8262),医疗图像和测试测量.本文介绍了Si5395/94/92主要特性,简化框图和框图,典型56G SerDes应用电路和同步线路卡SyncE电路图以及评估板Si5394 EVB主要特性,功能框图和电路图与材料清单.

The Si5395/94/92 Jitter attenuators combine fourth-generation DSPLL™ and Multi-Synth™ technologies to deliver ultra-low jitter (69 fs) for high performance applications like 56G SerDes. They are used in applications that demand the highest levelof integration and jitter performance. All PLL components are integrated on-chip,eliminating the risk of noise coupling associated with discrete solutions. Devicegrades J/K/L/M/E have an integrated reference to save board space, improve systemreliability and reduces the effect of acoustic emissions noise caused by temperatureramps. Grades A/B/C/D/P use an external crystal (XTAL) or crystal oscillator(XO) reference.

The Si5395/94/92 support free-run, synchronous and holdover modes as well as enhancedhitless switching, minimizing the phase transients associated when switching between input clocks. These devices are programmable via a serial interface with incircuit programmable non-volatile memory (NVM) so they always power up with aknown frequency configuration. Programming the Si5395/94/92 is easy with SiliconLabs’ ClockBuilderTM Pro software. Factory preprogrammed devices are also available.

Si5395/94/92主要特性:

• Generates any combination of outputfrequencies from any input frequency
• Ultra low phase jitter:
• 69 fs RMS (Grade P)
• 71 fs RMS (Grade E)
• 85 fs RMS (integer mode)
• 100 fs RMS (fractional mode)
• Enhanced hitless switching minimizes outputphase transients (0.2 ns typ)
• Input frequency range
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Meets G.8262, E.8262.1 EEC Standards
• Status monitoring
• Si5395: 4 input, 12 output
• Si5394: 4 input, 4 output
• Si5392: 4 input, 2 output
• External reference: Grades A/B/C/D/P
• Integrated reference: Grades J/K/L/M/E
• Drop-in compatible with Si5345/44/42

Si5395/94/92应用:

• 56G/112G PAM4 SerDes clocking
• OTN muxponders and transponders
• 10/40/100/200/400G networking line cards
• 10/40/100/400 GbE Synchronous Ethernet (ITU-T G.8262)
• Medical imaging
• Test and measurement

图1. Si5395/94/92简化框图

图2. Si5395/94/92框图

Si5395/94/92详细特性如下:

• Generates any output frequency in any format from any inputfrequency
• External XTAL or XO reference (A/B/C/D/P)
• Integrated reference (J/K/L/M/E)
• Ultra-low phase jitter of 69 fs (P-Grade)
• Dynamic phase adjust
• Input frequency range
• Differential: 8 kHz–750 MHz
• LVCMOS: 8 kHz–250 MHz
• Output frequency range
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz
• Meets requirements of:
• ITU-T G.8262 (SyncE) EEC Options 1 and 2
• ITU-T G.8262.1 (Enhanced SyncE) eEEC
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal amplitude
• Status monitoring (LOS, OOF, LOL)
• Enhanced hitless switching for 8 kHz, 19.44 MHz, 25 MHz inputsand other frequencies
• Locks to gapped clock inputs
• Free-run and holdover modes
• Drop-in compatible with Si5345/44/42
• Optional zero delay mode
• Fast-lock acquisition for low nominal bandwidths
• Independent Frequency-on-the fly for each MultiSynth
• DCO mode: as low as 0.001 ppb step size
• Core voltage
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• Si5395: 4 input, 12 output
• Grade A/B/C/D/P: 64-QFN 9×9 mm
• Grade J/K/L/M/E: 64-LGA 9x9 mm
• Si5394: 4 input, 4 output
• Grade A/B/C/D/P: 44-QFN 7×7 mm
• Grade J/K/L/M/E: 44-LGA 7x7 mm
• Si5392: 4 input, 2 output
• Grade A/B/C/D/P: 44-QFN 7×7 mm
• Grade J/K/L/M/E: 44-LGA 7x7 mm
• Temperature range: –40 to +85 ℃
• Pb-free, RoHS-6 compliant

图3.典型56G SerDes应用电路

图4.同步线路卡SyncE电路图

评估板Si5394 EVB

The Si5394 EVB is used for evaluating the Si5394 Any-Frequency, Any-Output, Jitter- Attenuating Clock Multiplier. There are four different EVBs for the Si5394. There is a Grade A and Grade P board which both require an external reference. There is also a Grade J and Grade E board which have a reference internal to the chip. This user guide is intended for all versions of the Si5394 EVBs. The term Si5394 EVB is inclusive of all four different evaluation boards. The device grade and revision is distinguished by a white 1 inch x 0.187 inch label installed in the lower left hand corner of the board. In the example below, the label "SI5394A-A-EB" indicates the evaluation board has been assembled with an Si5394 device, Grade A, Revision A, installed. (For ordering purposes only, the terms “EB” and “EVB” refer to the board and the kit respectively. For the purpose of this document, the terms are synonymous in context.)

评估板Si5394 EVB主要特性:

• Si5394A-A-EVB for evaluating externalreference versions Si5394A/B/C/D
• Si5394J-A-EVB for evaluating internalreference versions Si5394J/K/L/M
• Si5394P-A-EVB for evaluating externalreference (precision grade)
• Si5394E-A-EVB for evaluating internalreference (precision grade)
• Powered from USB port or external powersupply
• Onboard 48 MHz XTAL or Reference SMAInputs allow holdover mode of operation on the Si5394 Grade A and P
• ClockBuilder Pro® (CBPro) GUIprogrammable VDD supply allows device tooperate from 3.3 V, 2.5 V, or 1.8 V
• CBPro GUI programmable VDDO suppliesallow each of the 4 outputs to have its own power supply voltage selectable from 3.3V,2.5V, or 1.8 V
• CBPro GUI-controlled voltage, current, andpower measurements of VDD and all VDDO supplies
• Status LEDs for power supplies and control/status signals of Si5394
• SMA connectors for input clocks, outputclocks, and optional external timingreference clock to be used on externalreference grades only

图5.评估板Si5394 EVB外形图

图6.评估板Si5394 EVB功能框图

图7.评估板Si5394 EVB连接图

图8.评估板Si5394 EVB电路图(1)

图9.评估板Si5394 EVB电路图(2)

图10.评估板Si5394 EVB电路图(3)

图11.评估板Si5394 EVB电路图(4)

图12.评估板Si5394 EVB电路图(5)

图13.评估板Si5394 EVB电路图(6)

图14.评估板Si5394 EVB电路图(7)

图15.评估板Si5394 EVB电路图(8)

图16.评估板Si5394 EVB电路图(9)

图17.评估板Si5394 EVB电路图(10)

图18.评估板Si5394 EVB电路图(11)

图19.评估板Si5394 EVB电路图(12)

图20.评估板Si5394 EVB电路图(13)

图21.评估板Si5394 EVB电路图(14)

图22.评估板Si5394 EVB电路图(15)

图23.评估板Si5394 EVB电路图(16)

图24.评估板Si5394 EVB电路图(17)

图25.评估板Si5394 EVB电路图(18)

图26.评估板Si5394 EVB电路图(19)

图27.评估板Si5394 EVB电路图(20)

图28.评估板Si5394 EVB电路图(21)

图29.评估板Si5394 EVB电路图(22)

图30.评估板Si5394 EVB电路图(23)

图31.评估板Si5394 EVB电路图(24)

图32.评估板Si5394 EVB电路图(25)

图33.评估板Si5394 EVB电路图(26)

图34.评估板Si5394 EVB电路图(27)

图35.评估板Si5394 EVB电路图(28)

图36.评估板Si5394 EVB电路图(29)

图37.评估板Si5394 EVB电路图(30)

图38.评估板Si5394 EVB电路图(31)

图39.评估板Si5394 EVB电路图(32)

图40.评估板Si5394 EVB电路图(33)

图41.评估板Si5394 EVB电路图(34)

图42.评估板Si5394 EVB电路图(35)

图43.评估板Si5394 EVB电路图(36)

图44.评估板Si5394 EVB电路图(37)

图45.评估板Si5394 EVB电路图(38)

图46.评估板Si5394 EVB电路图(39)

图47.评估板Si5394 EVB电路图(40)

图48.评估板Si5394 EVB电路图(41)

图49.评估板Si5394 EVB电路图(42)

图50.评估板Si5394 EVB电路图(43)
评估板Si5394 EVB材料清单:






详情请见:
https://www.silabs.com/documents/public/data-sheets/si5395-94-92-a-datasheet.pdf
https://www.silabs.com/documents/public/user-guides/ug334-si5394evb.pdf
si5395-94-92-a-datasheet.pdf
ug334-si5394evb.pdf
si539x-design-files.zip

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