中国电子技术网

设为首页 网站地图 加入收藏

 

[原创] ST STM32MP157A高性能32位MPU开发方案

关键词:ARM Cortex-A7 MCU ARM Cortex-M4 MCU 消费类电子 医疗电子 白色家电

时间:2019-07-26 11:03:18       来源:中电网

ST公司的stm32MP157A是基于高性能双核Arm® Cortex®- A7 32位RISC核MPU,工作频率高达650MHz.Cortex®-A7处理器包括用于每个CPU的32KB L1指令缓存, 用于每个CPU的32KB L1数据缓存和256KB level2缓存.Cortex®-A7处理器是非常能效的应用处理器,在高端可穿戴设备和其它低功耗嵌入和消费应用中提供丰富的性能,比Cortex-A5提供多达20%的单线程性能,比Cortex-A9提供相仿的性能.STM32MP157A还嵌入了运行于高达533MHz的3D图像处理单元(Vivante® - OpenGL® ES 2.0),其性能高达26 Mtriangle/s,133 Mpixel/s.STM32MP157A还提供外接SDRAM接口,支持高达8G比特密度(1GB),16或32位高达533MHz的LPDDR2/LPDDR3或DDR3/DDR3L.所有器件提供两个ADC,两个DAC,一个低功耗RTC,12个通用16位计时器,两个用于马达控制的PWM计时器,一个真正随机号码发生器(RNG).器件支持用于外接sigma delta调制器(DFSDM)的六个数字滤波器,它们具有标准和高档通信接口.主要用在各种消费类,工业类,白色家电和医疗应用.本文介绍了STM32MP157A主要特性,框图,双核Arm® Cortex®-A7子系统主要特性,总线矩阵图和电源方案图,以及STM32MP157 MPU发现工具包STM32MP157C-DK2主要特性,硬件框图,电路图和材料清单.

The STM32MP157A devices are based on the high-performance dual-core Arm® Cortex®- A7 32-bit RISC core operating at up to 650 MHz. The Cortex-A7 processor includes a 32- Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.

The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex- A17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA®4 AXI bus interface.

The STM32MP157A devices also embed a Cortex® -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions and data types. The Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32MP157A devices also embed a 3D graphic processing unit (Vivante® - OpenGL® ES 2.0) running at up to 533 MHz, with performances up to 26 Mtriangle/s,133 Mpixel/s.

The STM32MP157A devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.

The STM32MP157A devices incorporate high-speed embedded memories with 708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access.

All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support six digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

• Standard peripherals
– Six I2Cs
– Four USARTs and four UARTs
– Six SPIs, three I2Ss full-duplex master/slave. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIF Rx interface
– Management data input/output slave (MDIOS)
– Three SDMMC interfaces
– An USB high-speed Host with two ports two high-speed PHYs and a USB OTG high-speed with full-speed PHY or high-speed PHY shared with second port of USB Host.
– Two FDCAN interface, including one supporting TTCAN mode
– A Gigabit Ethernet interface
– HDMI-CEC
• Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller
– A DSI Host interface.
A comprehensive set of power-saving mode allows the design of low-power applications. The STM32MP157A devices are proposed in 4 packages ranging from 257 to 448 balls with pitch 0.5 mm to 0.8 mm. The set of included peripherals changes with the device chosen.
These features make the STM32MP157A suitable for a wide range of consumer, industrial, white goods and medical applications.

STM32MP157A主要特性:

Core
• 32-bit dual-core Arm® Cortex®-A7
– L1 32-Kbyte I / 32-Kbyte D for each core
– 256-Kbyte unified level 2 cache
– Arm® NEON™ and Arm® TrustZone®
• 32-bit Arm® Cortex®-M4 with FPU/MPU
– Up to 209 MHz (Up to 703 CoreMark®)
Memories
• External DDR memory up to 1 Gbyte
– up to LPDDR2/LPDDR3-1066 16/32-bit
– up to DDR3/DDR3L-1066 16/32-bit
• 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + 64 KB of AHB SRAM in backup domain and 4 KB of SRAM in backup domain
• Dual mode Quad-SPI memory interface
• Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC
Security/safety
• TrustZone® peripherals, active tamper
• Cortex®-M4 resources isolation
Reset and power management
• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
• POR, PDR, PVD and BOR
• On-chip LDOs (RETRAM, BKPSRAM, DSI 1.2 V, USB 1.8 V, 1.1 V)
• Backup regulator (~0.9 V)
• Internal temperature sensors
• Low-power modes: Sleep, Stop and Standby
• LPDDR2/3 retention in Standby mode
• Controls for PMIC companion chip
Low-power consumption
• Total current consumption down to 6 μA
Clock management
• Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
• External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
• 6 × PLLs with fractional mode
General-purpose input/outputs
• Up to 176 I/O ports with interrupt capability
– Up to 8 secure I/Os
– Up to 6 Wakeup, 3 Tamper, 1 Active- Tamper
Interconnect matrix
• 2 bus matrices
– 64-bit Arm® AMBA® AXI interconnect, up to 266 MHz
– 32-bit Arm® AMBA® AHB interconnect, up to 209 MHz
3 DMA controllers to unload the CPU
• 48 physical channels in total
• 1 × high-speed general-purpose master direct memory access controller (MDMA)
• 2 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management
Up to 37 communication peripherals
• 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
• 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
• 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock)
• 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
• SPDIF Rx with 4 inputs • HDMI-CEC interface
• MDIO Slave interface
• 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
• 2 × CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN)
• 2 × USB 2.0 high-speed Host + 1 × USB 2.0 full-speed OTG simultaneously
– or 1 × USB 2.0 high-speed Host + 1 × USB 2.0 high-speed OTG simultaneously
• 10/100M or Gigabit Ethernet GMAC
– IEEE 1588v2 hardware, MII/RMII/GMII/RGMII
• 8- to 14-bit camera interface up to 140 Mbyte/s
6 analog peripherals
• 2 × ADCs with 16-bit max. resolution (12 bits 5 Msps, 14 bits 4.4 Msps, 16 bits 250 ksps)
• 1 × temperature sensor
• 2 × 12-bit D/A converters (1 MHz)
• 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters
• Internal or external ADC/DAC reference VREF+
Graphics
• 3D GPU: Vivante® - OpenGL® ES 2.0
– Up to 26 Mtriangle/s, 133 Mpixel/s
• LCD-TFT controller, up to 24-bit // RGB888
– up to WXGA (1366 × 768) @60 fps
– Two layers with programmable colour LUT
• MIPI® DSI 2 data lanes up to 1 GHz each
Up to 29 timers and 3 watchdogs
• 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 2 × 16-bit advanced motor control timers
• 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
• 5 × 16-bit low-power timers
• RTC with sub-second accuracy and hardware calendar
• 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
• 1 × SysTick M4 timer
• 3 × watchdogs (2 × independent and window)
Hardware acceleration
• HASH (MD5, SHA-1, SHA224, SHA256), HMAC
• 2 × true random number generator (3 oscillators each)
• 2 × CRC calculation unit
Debug mode
• Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
• 8-Kbyte embedded trace buffer
3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
All packages are ECOPACK®2 compliant

图1.STM32MP157A框图

双核Arm® Cortex®-A7子系统

The Cortex-A7 processor is a very energy-efficient applications processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20 % more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9. The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex- A17 processors, including virtualization support in hardware, NEON™, and 128-bit AMBA®4 AXI bus interface. The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this, there is improved branch prediction and improved memory system performance, with 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing.

双核Arm® Cortex®-A7子系统主要特性:

• ARMv7-A architecture
• 32-Kbyte L1 instruction cache for each CPU
• 32-Kbyte L1 data cache for each CPU
• 256-Kbyte level2 cache
• Arm® + Thumb®-2 instruction set
• Arm® TrustZone® security technology
• Arm® NEON™ Advanced SIMD
• DSP and SIMD extensions
• VFPv4 floating-point
• Hardware virtualization support
• Embedded trace module (ETM)
• Integrated generic interrupt controller (GIC) with 256 shared peripheral interrupts
• Integrated generic timer (CNT)

Arm® Cortex®-M4 with FPU

The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

Graphic processing unit (GPU)

The STM32MP157A includes a 3D graphics engine (Vivante). The GPU is a dedicated graphics processing unit accelerating numerous 3D graphics applications such as graphical user interface (GUI), menu display or animations. It works together with an optimized software stack design for industry-standard APIs with support for Android™ and Linux® embedded development platforms.

Hardware features:

• OpenGL ES 2.0 / 1.1 compliance, including extensions; OpenVG 1.1
• IEEE 32-bit floating-point pipeline
• Ultra-threaded, unified vertex and fragment (pixel) shaders
• Low memory bandwidth at both high and low data rates
• Low CPU loading
• Up to 12 programmable elements per vertex
• Dependent texture operation with high-performance
• Alpha blending
• Depth and stencil compare
• Support for 8 fragment shader simultaneous textures
• Support for 4 vertex shader simultaneous textures
• Point sampling, bi-linear sampling, tri-linear filtering, and cubic textures
• 8 k x 8 k texture size and 8 k x 8 k rendering target
• 4 Vertex DMA streams
API support:
• OpenGL ES 1.1 and 2.0
• OpenVG 1.1
• EGL 1.4
• OpenGL 2.1
Performance up to:
• 26 Mtriangle/s
• 133 Mpixel/s

图2. STM32MP157A总线矩阵图

图3. STM32MP157A电源方案图

STM32MP157 MPU发现工具包STM32MP157A-DK1和STM32MP157C-DK2

The STM32MP157A-DK1 and STM32MP157C-DK2 Discovery kits are designed as complete demonstration and developmentplatforms for STMicroelectronics Arm®-based dual Cortex®-A7 32 bits and Cortex®-M4 32 bits MPUs in the STM32MP1 Seriesand their STPMIC1 companion chip. They leverage the capabilities of STM32MP1 Series microprocessors to allow usersdevelop applications using STM32 MPU OpenSTLinux Distribution software (such as STM32MP1Starter) for the main processorand STM32CubeMP1 software for the co-processor.

They feature 16-bit DDR3L 4 Gbits at 533 MHz, MIPI DSISM 2 lanes at 1 Gbps, USB Type-C™ DRP HS port, USB Type-A HostHS ports, audio codec with analog audio input / output, microSD™ card high-speed mode up to 50 MHz, Gigabit Ethernet,HDMI® up to 720p60 (1280 × 720), 40-pin extended GPIOs, Arduino™, Wi‑Fi® 802.11b/g/n, Bluetooth® Low Energy 4.1, and STLINK/V2.1 (UART console).

The STM32MP157C-DK2, shown with display removed in Figure 4and Figure 5, is used as a reference design for userapplication development. It cannot be considered as the hardware design of a final application.

The hardware features of the Discovery kits are available for users to develop their applications: USB, Ethernet, LTDC, TFTLCD MIPI DSISM, microSD™ card, audio codec, user buttons, Wi‑Fi®, and Bluetooth® Low Energy. Extension headers allow easyconnection of an Arduino™ board for a specific application.An ST-LINK/V2-1 is integrated on the board, as embedded in-circuit debugger and programmer for the STM32 MPU and theUSB Virtual COM port bridge.


图4. STM32MP157C-DK2正面视图

图5. STM32MP157C-DK2背面视图

STM32MP157C-DK2主要特性:

Common features
– STM32MP157 Arm®-based dual Cortex®-A7 32 bits + Cortex®-M4 32 bits MPU in TFBGA361 package
– ST PMIC STPMIC1
– 4-Gbit DDR3L, 16 bits, 533 MHz
– 1-Gbps Ethernet (RGMII) compliant with IEEE-802.3ab
– USB OTG HS
– Audio codec
– 4 user LEDs
– 2 user and reset push-buttons, 1 wake-up button
– 5 V/3 A USB Type-C™power supply input (not provided)
– Board connectors:
◦ Ethernet RJ45
◦ 4 × USB Host Type-A
◦ USB Type-C™ DRP
◦ MIPI DSISM
◦ HDMI®
◦ Stereo headset jack including analog microphone input
◦ microSD™ card
◦ GPIO expansion connector (Raspberry Pi® shields capability)
◦ Arduino™ Uno V3 expansion connectors
– On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: Virtual COM portand debug port
– STM32CubeMP1 and full mainline open-source Linux® STM32 MPU OpenSTLinux Distribution (suchas STM32MP1Starter) software and examples
– Support of a wide choice of Integrated Development Environments (IDEs) including IAR™, Keil®, GCCbasedIDEs
• Board-specific features
– 4" TFT 480×800 pixels with LED backlight, MIPI DSISM interface, and capacitive touch panel
– Wi‑Fi® 802.11b/g/n
– Bluetooth® Low Energy 4.1

图6. STM32MP157x-DKx硬件框图

图7. STM32MP157x-DKx PCB布局图:顶层

图8. STM32MP157x-DKx PCB布局图:底层

图9. STM32MP157x-DKx电路图(1)

图10. STM32MP157x-DKx电路图(2)

图11. STM32MP157x-DKx电路图(3)

图12. STM32MP157x-DKx电路图(4)

图13. STM32MP157x-DKx电路图(5)

图14. STM32MP157x-DKx电路图(6)

图15. STM32MP157x-DKx电路图(7)

图16. STM32MP157x-DKx电路图(8)

图17. STM32MP157x-DKx电路图(9)

图18. STM32MP157x-DKx电路图(10)

图19. STM32MP157x-DKx电路图(11)

图20. STM32MP157x-DKx电路图(12)

图21. STM32MP157x-DKx电路图(13)

图22. STM32MP157x-DKx电路图(14)
STM32MP157x-DKx材料清单见:
MB1272-DK1-C01_BOM.xls
MB1272-DK2-C01_BOM.xls
详情请见:
https://www.st.com/content/ccc/resource/technical/document/user_manual/group1/d6/59/df/e0/8f
/e7/45/8f/DM00591354/files/DM00591354.pdf/jcr:content/translations/en.DM00591354.pdf

https://www.st.com/content/ccc/resource/technical/layouts_and_diagrams/schematic_pack/group0/
36/8e/ea/7a/ca/ca/4b/e4/mb1272-dk2-c01_schematic/files/MB1272-DK2-C01_Schematic.pdf/jcr:content/translations/en.MB1272-DK2-C01_Schematic.pdf

en.MB1272-DK2-C01_Schematic.pdf
stm32mp157a-dk1.pdf
en.DM00591354.pdf

  • 分享到:

 

猜你喜欢