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[原创] Cypress PSoC 4200-L可升级和配置平台开发方案

关键词:MHz ARM Cortex-M0 MCU PSoC Bluetooth Low Energy (BLE)

时间:2019-06-26 11:15:27       来源:中电网

Cypress公司的PSoC 4200-L是可升级和可配置平台架构,是采用ARM® Cortex®-M0 CPU的可编程嵌入系统控制器系列产品,组合了可编程和可配置模拟与数字区块以及灵活自动布线.基于这个平台的PSoC 4200L系列产品组合了具有数字可编程逻辑,可编程模拟,可编程互连,片外安全扩展存储器,高性能模数转换器,带比较模式的运放以及标准通信和定时外设.ARM Cortex-M0 CPU工作频率48MHz,具有单周期乘法,有带读加速器的多达256KB闪存,多达32KB SRAM以及32路的DMA引擎,低功耗1.71V-5.5V工作,带GPIO引脚叫醒的20nA暂停模式,蛰伏和深睡眠模式允许叫醒时间和功耗相权衡.PSoC 4 BLE为运动和健身监测,可穿戴,医疗设备,家庭自动化系统,物联网(IoT)低功耗系统提供了完整解决方案.本文介绍了PSoC 4200-L主要特性,框图,SAR ADC系统框图,MCU时钟架构图,以及蓝牙低功耗(BLE)Pioneer评估板套件CY8CKIT-042-BLE-A主要特性,包括BLE Dongle板,BLE Pioneer板和PSoC 4 BLE模块的框图,电路图,材料清单和蔼PCB设计图.

PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with anARM® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. ThePSoC 4200L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, programmable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion,opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200L products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digitalsubsystems allow flexibility and in-field tuning of the design.

PSoC 4200-L主要特性:

32-bit MCU Subsystem
■ 48 MHz ARM Cortex-M0 CPU with single-cycle multiply
■ Up to 256 kB of flash with Read Accelerator
■ Up to 32 kB of SRAM
■ DMA engine with 32 channels
Programmable Analog
■ Fouropamps that operate in Deep Sleep mode at very lowcurrent levels
■ Allopamps have reconfigurable high current pin-drive,high-bandwidth internal drive, ADC input buffering, andComparator modes with flexible connectivity allowing input
connections to any pin
■ Four current DACs (IDACs) for general-purpose or capacitivesensing applications on any pin
■ Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
■ Eight programmable logic blocks, each with 8 Macrocells andan 8-bit data path (called universal digital blocks or UDBs)
■ Cypress-provided peripheral component library, user-definedstate machines, and Verilog input
Low Power 1.71 V to 5.5 V Operation
■ 20-nA Stop Mode with GPIO pin wakeup
■ Hibernate and Deep Sleep modes allow wakeup-time versuspower trade-offs
Capacitive Sensing
■ Two Cypress Capacitive Sigma-Delta (CSD) blocks providebest-in-class SNR (>5:1) and water tolerance
■ Cypress-supplied software component makes capacitivesensing design easy
■ Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■ LCD drive supported on any pin with up to a maximum of 64outputs (common or segment)
■ Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
■ Four independent run-time reconfigurable serial communicationblocks (SCBs) with reconfigurable I2C, SPI, or UARTfunctionality
■ USB Full-Speed device interface 12 Mbits/sec with BatteryCharger Detect capability
■ Two independent CAN blocks for industrial and automotivenetworking
Timing and Pulse-Width Modulation
■ Eight 16-bit timer/counter pulse-width modulator (TCPWM)blocks
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals for motor drive andother high-reliability digital logic applications
Up to 98 Programmable GPIOs
■ 124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFNpackages
■ Any of up to 94 GPIO pins can be CapSense, analog, or digital
■ Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
■ Integrated Development Environment (IDE) providesschematic design entry and build (with analog and digitalautomatic routing)
■ Applications Programming Interface (API component) for allfixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■ After schematic entry, development can be done withARM-based industry-standard development tools

图1.PSoC 4200-L框图

图2.PSoC 4200-L SAR ADC系统框图

图3.PSoC 4200-L MCU时钟架构图

蓝牙低功耗(BLE)Pioneer评估板CY8CKIT-042-BLE-A

Thank you for your interest in the CY8CKIT-042-BLE-A Bluetooth® Low Energy (BLE) Pioneer Kit.

The BLE Pioneer Kit enables customers to evaluate and develop BLE projects using the PSoC® 4 BLE device.Bluetooth SMART™ or Bluetooth Low Energy (BLE) is a full-featured, layered, communicationprotocol that includes a 2.4-GHz radio, a link layer, and an application layer. However, you do notneed to understand the complex protocol to implement your projects using PSoC 4 BLE. TheCypress BLE solution, which includes the device, the BLE Component, and the BLE firmware stackwill take care of it for you. The Cypress BLE firmware stack is royalty free.

You will use two software tools, PSoC Creator™ and CySmart Central Emulation Tool, to developand debug your BLE project. PSoC Creator is Cypress’ standard integrated design environment(IDE). The BLE protocol has been abstracted into an easy drag-and-drop BLE Component in PSoCCreator. The CySmart Central Emulation Tool is a host tool for Windows PCs, which provides aneasy-to-use GUI to enable customers to test and debug their BLE projects.

The BLE Pioneer Kit offers footprint-compatibility with Arduino™ shields as well as 6-pin Digilent®Pmod™ daughter cards. In addition, the kit features a CapSense® slider, an RGB LED, a pushbuttonswitch, an onboard programmer/debugger and the USB-UART/I2C bridge functionality block(KitProg), a coin cell battery holder, and a Cypress F-RAM™. The BLE Pioneer Kit supports 1.9 V,3 V, 3.3 V, or 5 V as operating voltages. The BLE Pioneer Kit supports the PSoC4 BLE device whichis a 32-bit, 48-MHz Arm® Cortex®-M0 BLE solution with CapSense, 12-bit analog front end (1x SARADC, 4x low-power opamps, 2x low-power comparators, and 2x current DACs), 4x TCPWM1, 2x SCBs2, 4x UDBs3, LCD4, I2S5, and 36 GPIOs.PSoC 4 BLE provides a complete solution for sportsand fitness monitors, wearable electronics, medical devices, home automation systems, and sensorbasedlow-power systems for the Internet of Things (IoT).

The PSoC 4 BLE is available in 128KB and 256KB flash configurations. The PSoC 4 BLE issupported by royalty-free protocol stacks compatible with Bluetooth 4.1 and Bluetooth 4.2.

The BLE Pioneer Kit contains the following items:
■ BLE Pioneer Baseboard preloaded with the CY8CKIT-143A PSoC 4 BLE 256KB Module
■ CY5677 CySmart BLE 4.2 USB Dongle (BLE Dongle)
■ Quick start guide
■ USB Standard-A to Mini-B cable
■ Four jumper wires (4 inch) and two proximity sensor wires (5 inch)
■ Coin cell (3 V CR2032)

图4.Pioneer评估板套件CY8CKIT-042-BLE-A外形图

图5.BLE Pioneer基板CY8CKIT-042-BLE-A外形图

数字所对应内容:

1. RGB LED
2. BLE device reset button
3. CapSense proximity header
4. User button
5. CapSense slider
6. Arduino-compatible I/O headers (J2/J3/J4)
7. Arduino-compatible power header (J1)
8. DigilentPmod-compatible I/O header (J5)
9. Cypress F-RAM 1 Mb (FM24V10-G)
10.PSoC 5LP I/O header (J8)
11. PSoC 5LP programmer and debugger (CY8C5868LTI-LP039)
12.Coin cell holder (bottom side)
13.USB connector (J13)
14.Power LED and Status LED
15.System power supply jumper (J16) - LDO 1.9 V~5 V
16.BLE power supply jumper / current measurement (J15)
17.BLE module headers (J10/J11)

图5.BLE Pioneer基板CY8CKIT-042-BLE-A框图

图6.PSoC 4 BLE模块框图

图7. BLE Dongle框图

图8.BLE Dongle板电路图(1)

图9.BLE Dongle板电路图(2)

图10.BLE Dongle板电路图(3)
BLE Dongle PCBA BOM

图11.BLE Dongle板PCBA设计图(1)

图12.BLE Dongle板PCBA设计图(2)

图13.BLE Dongle板PCBA设计图(3)

图14.BLE Dongle板PCBA设计图(4)

图15.BLE Dongle板PCBA设计图(5)

图16.BLE Dongle板PCBA设计图(6)

图17.BLE Dongle板PCBA设计图(7)
BLE Pioneer Board PCBA BOM

图18.BLE Pioneer板电路图(1)

图19.BLE Pioneer板电路图(2)

图20.BLE Pioneer板电路图(3)

图21.BLE Pioneer板电路图(4)

图22.BLE Pioneer板PCB设计图(1)

图23.BLE Pioneer板PCB设计图(2)

图24.BLE Pioneer板PCB设计图(3)

图25.BLE Pioneer板PCB设计图(4)

图26.BLE Pioneer板PCB设计图(5)

图27.BLE Pioneer板PCB设计图(6)

图28.BLE Pioneer板PCB设计图(7)

图29.BLE Pioneer板PCB设计图(8)

图30.BLE Pioneer板PCB设计图(9)

图31.BLE Pioneer板PCB设计图(10)

图32.PSoC 4 BLE模块电路图(1)

图33.PSoC 4 BLE模块电路图(2)

图34.PSoC 4 BLE模块PCB设计图(1)

图35.PSoC 4 BLE模块PCB设计图(2)

图36.PSoC 4 BLE模块PCB设计图(3)

图37.PSoC 4 BLE模块PCB设计图(4)

图38.PSoC 4 BLE模块PCB设计图(5)

图39.PSoC 4 BLE模块PCB设计图(6)

图40.PSoC 4 BLE模块PCB设计图(7)

图41.PSoC 4 BLE模块PCB设计图(8)

图42.PSoC 4 BLE模块PCB设计图(9)

图43.PSoC 4 BLE模块PCB设计图(10)

图44.PSoC 4 BLE模块PCB设计图(11)
BLE Dongle板材料清单见:
BLE Dongle PCBA BOM.xls

BLE Pioneer板材料清单见:
BLE Pioneer Board PCBA BOM.xls

PSoC 4 BLE模块材料清单见:
PSoC 4 BLE Module PCBA BOM.xls

详情请见:
https://www.cypress.com/file/222206/download
https://www.cypress.com/file/222211/download
以及https://www.cypress.com/file/234851/download
https://www.cypress.com/file/458096/download
https://www.cypress.com/file/457861/download
https://www.cypress.com/file/458091/download
BLE Dongle Schematic_0.pdf
BLE Pioneer Board Schematic_0.pdf
BLE Pioneer Board Schematic.pdf
001-91686_PSOC_4_PSOC_4200-L_FAMILY_DATASHEET.pdf
002-00064_PSoC_R_4_PSoC_4200_L_Family_Datasheet_Programmable_System_on_Chip_PSoC_R_Preliminary_Chinese.pdf
CY8CKIT-042_PSoC_4_Pioneer_Kit_Guide_ZH.pdf
CY8CKIT-042-BLE_A_Board_Design_Files(Schematic,Layout,Gerber,BOM).zip

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