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[原创] TI DP83822低功耗单端10/100Mbps以太网PHY解决方案

关键词:网络通信 10/100Mbps以太网PHY DP83822

时间:2018-10-08 13:50:44       作者:TI       来源:中电网

TI公司的DP83822是低功耗单端10/100Mbps以太网PHY,提供所有在标准双绞线电缆或连接到外部光纤收发器发送和接收数据所有的物理层功能,另外通过标准MII,RMII或RGMII接口连接到MAC,还集成了电缆诊断工具,内置自测试以及容易使用的回送能力,支持多种工业总线,主要用在工业网络和工厂自动化,马达和运动控制,IP网络照相机和建筑物自动化.本文介绍了DP83822主要特性,框图和应用电路,以及评估板DP83822 EVM主要特性,框图,电路图,材料清单和PCB设计图.

The DP83822 is a low power single-port 10/100 Mbps Ethernet PHY. It provides all physical layer functions needed to transmit and receive data over both standard twisted-pair cables or connect to an external fiber optic transceiver. Additionally, the DP83822 provides flexibility to connect to a MAC through a standard MII, RMII, or RGMII interface.

The DP83822 offers integrated cable diagnostic tools, built-in self-test, and loopback capabilities for ease of use. It supports multiple industrial buses with its fast link-down timing as well as Auto-MDIX in forced modes.

The DP83822 offers an innovative and robust approach for reducing power consumption through EEE, WoL and other programmable energy savings modes.

The DP83822 is a feature rich and pin-to-pin upgradeable option for the TLK105, TLK106,TLK105L and TLK106L 10/100 Mbps Ethernet PHYs.

The DP83822 comes in a 32-pin 5.00-mm × 5.00-mm VQFN package.

DP83822主要特性:

• IEEE 802.3u Compliant: 100BASE-FX, 100BASETX and 10BASE-Te
• MII / RMII / RGMII MAC Interfaces
• Low Power Single Supply Options:
– 1.8-V AVD < 120 mW
– 3.3-V AVD < 220 mW
• ±16-kV HBM ESD Protection
• ±8-kV IEC 61000-4-2 ESD Protection
• Start of Frame Detect for IEEE 1588 Time Stamp
• Fast Link-Down Timing
• Auto-Crossover in Force Modes
• Operating Temperature: –40℃ to +125℃
• I/O Voltages: 3.3 V, 2.5 V, and 1.8 V
• Power Savings Features
– Energy Efficient Ethernet (EEE) IEEE 802.3az
– WoL (Wake-on-LAN) Support With Magic Packet Detection
– Programmable Energy Savings Modes
• Cable Diagnostics
• BIST (Built-In Self-Test)
• MDC / MDIO Interface

DP83822应用:

• Industrial Networks and Factory Automation
• Motor and Motion Control
• IP Network Cameras
• Building Automation

图1. DP83822功能框图

图2. DP83822简化电路图

图3. DP83822典型应用电路图

图4. DP83822 TPI网络电路图

图5. DP83822光纤网络电路图

评估板DP83822 EVM

The DP83822 EVM supports 10/100 Mbps and is compliant to the IEEE 802.3u standard. This reference design supports MII, RMII and RGMII MAC interfaces.

The DP83822 EVM includes two onboard status LEDs, optional Fiber SFP connector and cage, and onboard supply through a 5-V micro USB connector. The DP83822 EVM is capable of providing a 125-MHz, 50-MHz or 25-MHz reference clock from an onboard 25-MHz crystal. The EVM includes the CDCE925 programmable 2-PLL VCXO clock synthesizer with 1.8-V to 3.3-V LVCMOS outputs. Serial management interface, MDIO/MDC, is supported and can be used to access PHY registers for additional features. There are 4-level straps, which allow for system configurations without the need to directly access PHY registers. External power supplies can be connected to each specified voltage rail for additional system evaluation. The DP83822 supports Wake-on-LAN, Energy Efficient Ethernet (IEEE802.3az), Start-of-Frame Detect IEEE 1588 Time Stamp, and configurable I/O voltages.

评估板DP83822 EVM主要特性:

• IEEE 802.3u Compliant: 100BASE-FX, 100BASE-TX and 10BASE-Te
• CDCE925 Programmable 2-PLL VCXO Clock Synthesizer with 1.8 V to 3.3 V
• MII, RMII and RGMII MAC interfaces
• SFD IEEE 1588 Time Stamp
• Two status LEDs
– LED LINK/ACTIVITY
– LED SPEED
• Low Power Modes
– Energy Efficient Ethernet (IEEE802.3az)
– Wake-on-LAN
– Active Sleep
– Passive Sleep
– IEEE Power Down
– Deep Power Down
• Variable I/O voltage range: 1.8 V, 2.5 V and 3.3 V
• 100BASE-TX error free data transfer over 150 meters on CAT5 cable
The DP83822 EVM has an RJ45 connector (J12) with discrete magnetics and stuffing resistor array for configurable bootstraps. Customers are encouraged to use a design similar to the EVM circuit to expedite their product development.

图6. DP83822 10/100Mbps以太网PHY EVM外形图

图7.评估板DP83822 EVM正面图

图8.评估板DP83822 EVM背面图

图9.评估板DP83822 EVM框图

图10.评估板DP83822 EVM硬件电路图

图11.评估板DP83822 EVM主区块电路图

图12.评估板DP83822 EVM电源部分电路图

图13.评估板DP83822 EVM模拟前端电路

图14.评估板DP83822 EVM连接器和引导程序电路图
评估板DP83822 EVM材料清单:




图15.评估板DP83822 EVM PCB设计图(1):顶层综合

图16.评估板DP83822 EVM PCB设计图(2):顶层

图17.评估板DP83822 EVM PCB设计图(3):信号层1

图18.评估板DP83822 EVM PCB设计图(4):信号层2

图19.评估板DP83822 EVM PCB设计图(5):信号层3

图20.评估板DP83822 EVM PCB设计图(6):信号层4

图21.评估板DP83822 EVM PCB设计图(7):底层

图22.评估板DP83822 EVM PCB设计图(8):底层综合

图23.评估板DP83822 EVM PCB设计图(9):顶层装配

图24.评估板DP83822 EVM PCB设计图(10):底层装配
详情请见:
http://www.ti.com/lit/ds/symlink/dp83822if.pdf
http://www.ti.com/lit/ug/snlu179/snlu179.pdf
dp83822if (4).pdf
snlu179.pdf

 

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