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[原创] NXP KW41Z超低功耗SoC开发方案

关键词:ARM Cortex-M0+MCU SoC 低功耗蓝牙(BLE)

时间:2017-03-06 13:24:57       作者:NXP       来源:中电网

NXP公司的KW41Z/31Z/21Z是超低功耗高度集成的单片器件,集成了无线收发器,工作频率2.36 GHz 到 2.48 GHz,支持SK/GFSK和O-QPSK调制;还集成了ARM Cortex-M0+ CPU,高达512KB闪存和高达128KB SRAM,BLE连接层硬件,802.15.4包处理器硬件和外设,主要用在手持保健设备,可穿戴运动和健身设备,AV遥控,计算机键盘和鼠标,游戏控制器,接入控制,安全系统,智能和家用区域网路.本文介绍了KW41Z/31Z/21Z主要特性,框图以及Freedom开发板FRDM-KW41Z主要

The KW41Z/31Z/21Z (called KW41Z throughout this document) is an ultra lowpower,
highly integrated single-chip device that enables Bluetooth low energy (BLE),
Generic FSK (at 250, 500 and 1000 kbps) or IEEE Standard 802.15.4 RF connectivity
for portable, extremely low-power embedded systems. Applications include portable
health care devices, wearable sports and fitness devices, AV remote controls,
computer keyboards and mice, gaming controllers, access control, security systems,
smart energy and home area networks.

The KW41Z SoC integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz
range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM Cortex-
M0+ CPU, up to 512 KB Flash and up to 128 KB SRAM, BLE Link Layer hardware,
802.15.4 packet processor hardware and peripherals optimized to meet the
requirements of the target applications.

The KW41Z SoC’s radio frequency transceiver is compliant with Bluetooth version
4.2 for Low Energy (aka Bluetooth Smart or BLE), Generic FSK and the IEEE
Standard 802.15.4 using O-QPSK in the 2.4 GHz ISM band. NXP provides fully
certified Bluetooth Low Energy and IEEE Standard 802.15.4 protocol stacks,
including Thread, and application profiles to support KW41Z.

The KW41Z SoC can be used in applications as a "BlackBox" modem by simply
adding BLE or IEEE Standard 802.15.4 connectivity to an existing embedded controller system, or used as a stand-alone smart wireless sensor with embedded application where no host controller is required.

KW41Z has 512/256 KB of on-chip Flash and 128/64 KB of on-chip SRAM memory available to be used by customer applications and chosen communication protocol stack using a choice of either NXP or 3rd party software development tools.

The RF section of the KW41Z SoC is optimized to require very few external components, achieving the smallest RF footprint possible on a printed circuit board.

Extremely long battery life is achieved though efficiency of code execution in the Cortex-M0+ CPU core and the multiple low power operating modes of the KW41Z SoC. Additionally, an integrated DC-DC converter enables a wide operating range from 0.9 V to 4.2 V. The DC-DC in Buck mode enables KW41Z to operate from a single coin cell battery with a significant reduction of peak Rx and Tx current consumption. The DC-DC in boost mode enables a single alkaline battery to be used throughout its entire useful voltage range of 0.9 V to 1.795 V.

KW41Z主要特性:

多标准无线电:
• 2.4 GHz Bluetooth Low Energy ver. 4.2 compliant supporting up to 2 simultaneous hardware connections
• IEEE Std. 802.15.4 compliant with dual-PAN support
• Generic FSK modulation
• Data Rate: 250, 500 and 1000 kbps
• Modulations: GFSK BT = 0.3, 0.5, 0.7; FSK/MSK
• Modulation Index: 0.32, 0.5, or 0.7
• Typical Receiver Sensitivity (BLE) = -95 dBm
• Typical Receiver Sensitivity (802.15.4) = -100 dBm
• Typical Receiver Sensitivity (250 kbps GFSK-BT=0.5, h=0.5) = -100 dBm
• Prog Transmitter Output Power: -30 dBm to 3.5 dBm
• Low external component counts for low cost application
• On-chip balun with single ended bidirectional RF port
MCU和存储器
• Up to 48 MHz ARMR Cortex-M0+ core
• On-chip 512/256 KB Flash memory
• On-chip 128/64 KB SRAM
低功耗
• Transceiver current (DC-DC buck mode, 3.6 V supply)
• Typical Rx Current: 6.8 mA
• Typical Tx current: 6.1 mA (0 dBm output)
• Low Power Mode (VLLS0) Current: 182 nA
时钟
• 26 and 32 MHz supported for BLE and FSK modes
• 32 MHz supported for IEEE Standard 802.15.4
• 32.768 kHz Crystal Oscillator
工作特性
• Voltage range: 0.9 V to 4.2 V
• Temperature range: –40 to 105 °C
人机接口
• Touch sensing input
• General-purpose input/output
系统外设
?Nine MCU low-power modes to provide power optimization based on application requirements
?DC-DC Converter supporting Buck, Boost, and Bypass operating modes
?Direct memory access(DMA) Controller
?Computer operating properly(COP) watchdog
?Serial wire debug(SWD) Interface and Micro Trace buffer
?Bit Manipulation Engine (BME)
模拟模块
?16-bit Analog-to-Digital Converter (ADC)
?12-bit Digital-to-Analog Converter (DAC)
?6-bit High Speed Analog Comparator (CMP)
?1.2 V voltage reference (VREF)
计时器
?16-bit low-power timer (LPTMR)
?3 Timers Modules(TPM): One 4 channel TPM and two 2 channel TPMs
?Programmable Interrupt Timer (PIT)
?Real-Time Clock (RTC)
通信接口
?2 serial peripheral interface (SPI) modules
?2 inter-integrated circuit (I2C) modules
?Low Power UART module
?Carrier Modulator Timer (CMT)
安全
?AES-128 Hardware Accelerator (AESA)
?True Random Number Generator (TRNG)
?Advanced flash security
?80-bit unique identification number per chip
?40-bit unique media access control (MAC) subaddress
?Bluetooth-LE v4.2 Secure Connections
?IEEE Standard 802.15.4-2011 compliant security
无线电特性
Operating frequencies:
?2.4 GHz ISM band (2400-2483.5 MHz)
?MBAN 2360-2400 MHz
Supported standards:
?Bluetooth v4.2 Low Energy compliant 1 Mbps GFSK modulation supporting up
to 2 simultaneous connections in hardware (master-slave, master-master, slaveslave)
?IEEE Standard 802.15.4-2011 compliant O-QPSK modulation and security features
?Kinetis Thread Networking Stack
?Bluetooth Low Energy(BLE) Application Profiles
Receiver performance:
?Receive sensitivity of -95 dBm for BLE
?Receive sensitivity of -100 dBm typical for IEEE Standard 802.15.4
?Receive sensitivity of up to -100 dBm for a 250 kbps GFSK mode with a
modulation index of 0.5. Receive sensitivity in generic FSK modes depends on mode selection and data rate.
其它特性:
• Programmable transmit output power from -30 dBm to 3.5 dBm
• Integrated on-chip balun
• Single ended bidirectional RF port shared by transmit and receive
• Low external component count
• Supports transceiver range extension using external PA and/or LNA
• 26 and 32 MHz supported for BLE and FSK modes
• 32 MHz supported for IEEE Standard 802.15.4
• Bluetooth Low Energy ver. 4.2 Link Layer hardware with 2 independent hardware connection engines
• Hardware acceleration for IEEE Standard 802.15.4 packet processing/link layer
• Hardware acceleration for Generic FSK packet processing
• Supports dual PAN for IEEE Standard 802.15.4 with hardware-assisted address
matching acceleration
• Generic FSK modulation at 250, 500 and 1000 kbps
• Supports antenna diversity option for IEEE Std. 802.15.4

MCU特性:

ARM Cortex-M0+ CPU
• Up to 48 MHz CPU
• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
• Supports up to 32 interrupt request sources
• Binary compatible instruction set architecture with the Cortex-M0 core
• Thumb instruction set combines high code density with 32-bit performance
• Serial Wire Debug (SWD) reduces the number of pins required for debugging
• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
• 32 vectored interrupts, 4 programmable priority levels
• Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low power modes
?Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
?A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected
Debug Controller
?Two-wire Serial Wire Debug (SWD) interface
?Hardware breakpoint unit for 2 code addresses
?Hardware watchpoint unit for 2 data items
?Micro Trace Buffer for program tracing
On-Chip Memory
?512/256 KB Flash
?Firmware distribution protection. Flash can be marked execute-only on a persector
(8 KB) basis to prevent firmware contents from being read by 3rd parties
?Flash implemented as two equal blocks each of 256 KB block. Code can execute or read from one block while the other block is being erased or programmed
?128/64 KB SRAM
?Security circuitry to prevent unauthorized access to RAM and flash contents through the debugger
系统特性
Power Management Control Unit (PMC)
?Programmable power saving modes
?Available wake-up from power saving modes via internal and external sources
?Integrated Power-on Reset (POR)
?Integrated Low Voltage Detect (LVD) with reset (brownout) capability
?Selectable LVD trip points
?Programmable Low Voltage Warning (LVW) interrupt capability
?Individual peripheral clocks can be gated off to reduce current consumption
?Internal Buffered bandgap reference voltage
?Factory programmed trim for bandgap and LVD
?1 kHz Low Power Oscillator (LPO)
DC/DC转换器
• Internal switched mode power supply supporting Buck, Boost, and Bypass operating modes
• Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell battery operation (typical CR2032 cell).
• Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is efficiently increased to the static internal core voltage level, ideal for single battery operation (typical AA or AAA alkaline cell).
• When DC-DC is not used, the device supports an external voltage range of 1.5 V to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)
• An external inductor is required to support the Buck or Boost modes
• The DC-DC Converter 1.8 V output current drive for external devices (MCU in RUN mode, Radio is enabled, other peripherals are disabled)
• Up to 44 mA in buck mode with VDD_1P8 = 1.8 V
• Up to 31.4 mA in buck mode with VDD_1P8 = 3.0 V
DMA控制器
• Internal switched mode power supply supporting Buck, Boost, and Bypass operating modes
• Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell battery operation (typical CR2032 cell).
• Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is efficiently increased to the static internal core voltage level, ideal for single battery operation (typical AA or AAA alkaline cell).
• When DC-DC is not used, the device supports an external voltage range of 1.5 V to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)
• An external inductor is required to support the Buck or Boost modes
• The DC-DC Converter 1.8 V output current drive for external devices (MCU in RUN mode, Radio is enabled, other peripherals are disabled)
• Up to 44 mA in buck mode with VDD_1P8 = 1.8 V
• Up to 31.4 mA in buck mode with VDD_1P8 = 3.0 V
DMA控制器
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 4-channel implementation that performs complex data transfers with minimal intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration Count
• Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
DMA通路复接器(DMA MUX)
• 4 independently selectable DMA channel routers
• 2 periodic trigger sources available
• Each channel router can be assigned to 1 of the peripheral DMA sources
COP看门狗模块
• Independent clock source input (independent from CPU/bus clock)
• Choice between two clock sources
• LPO oscillator
• Bus clock
系统时钟
• Both 26 MHz and 32 MHz crystal reference oscillator supported for BLE and FSK radio modes
• 32 MHz crystal reference oscillator supported for IEEE 802.15.4 radio mode
• MCU can derive its clock either from the crystal reference oscillator or the frequency locked loop (FLL)
• 32/32.768 kHz crystal reference oscillator used to maintain precise Bluetooth radio time in low power modes
• Multipurpose Clock Generator (MCG)
• Internal reference clocks — Can be used as a clock source for other on-chip peripherals
• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy across full temperature range
• On-chip 4MHz oscillator with 5% accuracy across full temperature range
• Frequency-locked loop (FLL) controlled by internal or external reference
• 20 MHz to 48 MHz FLL output
独特的标识符
• 10 bytes(or 80-bits) of the Unique ID represents a unique identifier for each chip
• 40 bits of unique media access control (MAC) address, which can be used to build a unique 48-bit Bluetooth-LE or 64-bit IEEE 802.15.4 device address
外设特性
16-bit Analog-to-Digital Converter (ADC)
?Linear successive approximation algorithm with 16-bit resolution
?Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
?Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
?Single or continuous conversion
?Configurable sample time and conversion speed / power
?Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
?Input clock selection
?Operation in low power modes for lower noise operation
?Asynchronous clock source for lower noise operation
?Selectable asynchronous hardware conversion trigger
?Automatic compare with interrupt for less-than, or greater than, or equal to programmable value
?Temperature sensor
?Battery voltage measurement
?Hardware average function
?Selectable voltage reverence
?Self-calibration mode
12-Bit Digital-to-Analog Converter (DAC)
?12-bit resolution
?Guaranteed 6-sigma monotonicity over input word
?High- and low-speed conversions
?1  conversion rate for high speed, 2  for low speed
?Power-down mode
?Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth
?Automatic mode allows programmable period, update rate, and range
?DMA support with configurable watermark level
High-Speed Analog Comparator (CMP)
?6-bit DAC programmable reference generator output
?Up to eight selectable comparator inputs; each input can be compared with any
input by any polarity sequence
?Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• Operational in all MCU power modes except VLLS0 mode
基准电压(VREF1)
• Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset
• Programmable buffer mode selection:
• Off
• Bandgap enabled/standby (output buffer disabled)
• High power buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• VREF_OUT output signal
低功耗计时器(LPTMR)
• One channel
• Operation as timer or pulse counter
• Selectable clock for prescaler/glitch filter
• 1 kHz internal LPO
• External low power crystal oscillator
• Internal reference clock
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Functional in all power modes
计时器/PWM (TPM)
• TPM0: 4 channels, TPM1 and TPM2: 2 channels each
• Selectable source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Input capture and output compare modes
• Generation of hardware triggers
• TPM1 and TPM2: Quadrature decoder with input filters
• Global time base mode shares single time base across multiple TPM instances
可编程中断计时器(PIT)
• Up to 2 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
实时时钟(RTC)
• 32-bit seconds counter with 32-bit alarm
• Can be invalidated on detection of tamper detect
• 16-bit prescaler with compensation
• Register write protection
• Hard Lock requires MCU POR to enable write access
• Soft lock requires POR or software reset to enable write/read access
• Capable of waking up the system from low power modes
I2C
• Two channels
• Compatible with I2C bus standard and SMBus Specification Version 2 features
• Up to 400 kHz operation
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
LPUART
• One channel
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Programmable 1 or 2 stop bits
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Two receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection
• Operation in low power modes
• Hardware Flow Control RTSCTS
• Functional in Stop/VLPS modes
Serial Peripheral Interface (DSPI)
• Two independent SPI channels
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
• Four modes of operation
• Time; with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
• Hysteresis and configurable pull up device on all input pins
• Independent pin value register to read logic level on digital pin
• All GPIO pins can generate IRQ and wakeup events
• Configurable drive strength on some output pins
Touch Sensor Input (TSI)
• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
• Internal reference oscillator for high-accuracy measurement
• Configurable software or hardware scan trigger
• Capability to wake MCU from low power modes
• Compensate for temperature and supply voltage variations
• High sensitivity change with 16-bit resolution register
• Configurable up to 4096 scan times
• Support DMA data transfer
Keyboard Interface
• GPIO can be configured to function as a interrupt driven keyboard scanning matrix
• In the 48pin package there are a total of 26 digital pins
• These pins can be configured as needed by the application as GPIO, LPUART,
SPI, I2C, ADC, timer I/O as well as other functions
3.6 Security Features
Advanced Encryption Standard Accelerator(AES-128 Accelerator)
The advanced encryption standard accelerator (AESA) module is a standalone hardware
coprocessor capable of accelerating the 128-bit advanced encryption standard (AES)
cryptographic algorithms.
The AESA engine supports the following cryptographic features.
LTC includes the following features:
• Cryptographic authentication
• Message authentication codes (MAC)
• Cipher-based MAC (AES-CMAC)
• Extended cipher block chaining message authentication code (AESXCBC-MAC)
• Auto padding
• Integrity Check Value(ICV) checking
• Authenticated encryption algorithms
• Counter with CBC-MAC (AES-CCM)
• Galois counter mode (AES-GCM)
• Symmetric key block ciphers
• AES (128-bit keys)
• Cipher modes:
• AES-128 modes
• Electronic codebook (ECB)
• Cipher block chaining (CBC)
• Counter (CTR)
• DES modes
• Electronic codebook (ECB)
• Cipher block chaining (CBC)
• Cipher feedback (CFB)
• Output Feedback (OFB)
• Secure scan
True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is a hardware accelerator module that
constitutes a high-quality entropy source.
• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropyconsuming
module. , such as a deterministic random number generator.
• TRNG output can be read and used by a deterministic pseudo-random number
generator (PRNG) implemented in software.
• TRNG-PRNG combination achieves NIST compliant true randomness and
cryptographic-strength random numbers using the TRNG output as the entropy source.
• A fully FIPS 180 compliant solution can be realized using the TRNG together with a FIPS compliant deterministic random number generator and the SoC-level security.
Flash Memory Protection
The on-chip flash memory controller enables the following useful features:
• Program flash protection scheme prevents accidental program or erase of stored data.
• Program flash access control scheme prevents unauthorized access to selected code segments.
• Automated, built-in, program and erase algorithms with verify.
• Read access to one program flash block is possible while programming or erasing data in the other program flash block.

图1.KW41Z框图

Freedom开发板FRDM-KW41Z

 This user’s guide describes the hardware for the FRDM-KW41Z Freedom development board. The FRDM-KW41Z Freedom development board is a small, low-power, and cost-effective evaluation and development board for application prototyping and demonstration of the KW41Z/31Z/21Z (KW41Z) family of devices. These evaluation boards offer easy-to-use mass-storage-device mode flash programmer, a virtual serial port, and standard programming and run-control capabilities.

The KW41Z is an ultra-low-power, highly integrated single-chip device that enables Bluetooth Low Energy (BLE), Generic FSK (at 250, 500, and 1000 kbps) or IEEE Standard 802.15.4 with Thread support for portable, extremely low-power embedded systems.

The KW41Z integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM® Cortex®-M0+ CPU, up to 512 KB Flash and up to 128 KB SRAM, BLE Link Layer hardware, 802.15.4 packet processor hardware and peripherals optimized to meet the requirements of the target applications.

The FRDM-KW41Z development board is an evaluation environment supporting NXP’s KW41Z/31Z/21Z (KW41Z) Wireless Microcontrollers (MCU). The KW41Z integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz range (supporting a range of FSK/GFSK and O-QPSK modulations) and an ARM Cortex-M0+ MCU into a single package. NXP supports the KW41Z with tools and software that include hardware evaluation and development boards, software development IDE, applications, drivers, custom PHY usable with IEEE Std. 802.15.4 compatible MAC, and BLE Link Layer. The FRDM-KW41Z development board consists of the KW41Z device with a 32 MHz reference oscillator crystal, RF circuitry (including antenna), 4-Mbit external serial flash, and supporting circuitry in the popular Freedom board form-factor. The board is a standalone PCB and supports application development with NXP’s Bluetooth Low Energy, Generic FSK, and IEEE Std. 802.15.4 protocol stacks including Thread.


图2. Freedom开发板FRDM-KW41Z框图

图3. Freedom开发板FRDM-KW41Z外形图

图4. Freedom开发板FRDM-KW41Z元件配置图

Freedom开发板FRDM-KW41Z主要特性:

• NXP’s ultra-low-power KW41Z Wireless MCU supporting BLE, Generic FSK, and IEEE Std. 802.15.4 (Thread) platforms
• IEEE Std. 802.15.4-2006 compliant transceiver supporting 250 kbps O-QPSK data in 5.0 MHz channels, and full spread-spectrum encoding and decoding
• Fully compliant Bluetooth v4.2 Low Energy (BLE)
• Reference design area with small-footprint, low-cost RF node:
— Single-ended input/output port
— Low count of external components
— Programmable output power from -30 dBm to +3.5 dBm at the SMA connector, when using DCDC Bypass or operating the DCDC in Buck mode
— Receiver sensitivity is -100 dBm, typical (@1 % PER for 20-byte payload packet) for 802.15.4 applications, at the SMA connector
— Receiver sensitivity is -95 dBm (for BLE applications) at the SMA connector
• Integrated PCB inverted F-type antenna and SMA RF port (requires moving C7 to C8)
• Selectable power sources
• DC-DC converter with Buck, Boost, and Bypass operation modes
• 32 MHz reference oscillator
• 32.768 kHz reference oscillator
• 2.4 GHz frequency operation (ISM and MBAN)
• 4-Mbit (512 kB) external serial flash memory for Over-the-Air Programming (OTAP) support
• NXP FX)S8700CQ Digital Sensor, 3D Accelerometer (±2g/±4g/±8g) + 3D Magnetometer
• Integrated Open-Standard Serial and Debug Adapter (OpenSDA)
• Cortex 10-pin (0.05²) SWD debug port for target MCU
• Cortex 10-pin (0.05²) JTAG port for OpenSDA updates
• One RGB LED indicator
• One red LED indicator
• Two push-button switches
• Two TSI buttons (Touch Sensing Input electrodes)

图5. Freedom开发板FRDM-KW41Z电路图(1)

图6. Freedom开发板FRDM-KW41Z电路图(2)

图7. Freedom开发板FRDM-KW41Z电路图(3)
详情请见:
MKW41Z512.pdf?pspll=1">http://cache.nxp.com/assets/documents/data/en/data-sheets/MKW41Z512.pdf?pspll=1

http://www.nxp.com/assets/downloads/data/en/schematics/FRDM-KW41Z-SCH.pdf

FRDM-KW41Z-SCH.pdf

FRDMKW41ZUG.pdf

MKW41Z512.pdf

 

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