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[原创] Microsemi低功耗PolarFire FPGA开发方案

关键词:PolarFire FPGA SerDes IoT 无线通信 有线通信 工业4.0

时间:2017-02-21 13:05:43       作者:Microsemi       来源:中电网

Microsemi公司的PolarFire FPGA是第五代非易式FPGA器件,采用28nm非易式工艺技术,具有最低的功耗和中等范围密度,集成了最低功耗的FPGA架构,最低功耗的12.7 Gbps收发器,内置了低功耗双PCI Express Gen2 (EP/RP),选择数据安全器件和低功耗加密协处理器.工作电压1.0 V和1.05 V,主要用在有线接入网络,蜂窝基础设备,国防和商用航空领域,以及包括工业自动化和互联网(IoT)的工业4.0.本文介绍了PolarFire FPGA主要特性,框图以及PolarFire FPGA评估板硬件特性和详细电路图.

PolarFire™ FPGAs are the fifth generation family of non-volatile FPGA devices from Microsemi, built on state-of-the-art 28nm non-volatile process technology. Cost-optimized PolarFire FPGAs deliver the lowest power at mid-range densities. PolarFire FPGAs lower the cost of mid-range FPGAs by integrating the industry’s lowest power FPGA fabric, lowest power 12.7 Gbps transceiver lane, built-in low power dual PCI Express Gen2 (EP/RP), and, on select data security (S) devices, an integrated low-power crypto co-processor. PolarFire FPGAs can operate at 1.0 V and 1.05 V, offering the end user the ability to trade off power and performance to match the application requirements.
This document describes the features of PolarFire FPGAs Extended Commercial (0 °C to 100 °C) and Industrial (–40 °C to 100 °C) device offerings.

Cost-optimized Architecture

Architecture and process optimizations for 100K/500K LE devices
Transceiver performance optimized for 12.7 Gbps, which yields smaller size
1.6 Gbps I/Os—hardened I/O gearing logic with CDR (supports SGMII/GbE links on these GPIOs)
Best-in-class high-performance, hardened security IP in mid-range devices

Power Optimization

The lowest static power—1/10 static power vs. competing devices 
Transceiver optimized for 12.7 Gbps, which yields 1/2 the power vs. competing devices
Low power Flash*Freeze mode yields best-in-class standby power
Integrated hard IP—DDR PHY, PCIe endpoint/root port, crypto processor
Total power (static and dynamic)—up to 50% lower power

PolarFire FPGA主要特性:

• Up to 481K logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flip-flop
• 20 Kb dual- or two-port large static random access memory (LSRAM) block with a built-in single error correct double error detect (SECDED)
• 64 × 12 two-port μRAM block implemented as an array of latches
• 18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16 deep x 18 coefficient ROM
• Built-in μPROM, modifiable at program time, readable at run time for user data storage
• High-speed serial connectivity with built-in multi-gigabit multi-protocol transceivers from
250 Mbps to 12.7 Gbps
• Integrated dual PCIe for up to ×4 Gen 2 Endpoint (EP) and Root Port (RP) designs
• High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps LPDDR3/DDR3 memories with integrated I/O digital
• General purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps DDR3, and 1600 Mbps LVDS I/O speed with integrated I/O digital logic
• Low-power phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low-jitter
• Low-power features
• Low device static power
• Low inrush current
• Low power transceivers
• Unique Flash*Freeze (F*F) mode
• 1.0 V and 1.05 V operating modes
• Reliability features
• FPGA configuration cells single event upset (SEU) immune
• Built-in SECDED and memory interleaving on LSRAMs
• System controller suspend mode for safety-critical designs
• Security features
• Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA)
bitstream protection
• Integrated physically unclonable function (PUF)
• 56 KBytes of secure NVM (sNVM)
• Built-in tamper detectors and countermeasures
• Digest integrity check for FPGA, μPROM, and sNVM
• Data security features in S devices—true random number generator, integrated athena terafire EXP5200B crypto co-processor, suite B capable, and CRI DPA countermeasure pass-through license
• Libero® SoC PolarFire FPGA toolset
• Complete FPGA and embedded software development environment
• Includes Synplify Pro synthesis and Mentor ModelSim ME simulation
PolarFire FPGA Architecture 
PolarFire FPGAs deliver up to 500K logic elements, 12.7G transceivers at 50% lower power.

图1. PolarFire FPGA框图

PolarFire FPGA评估板

Microsemi's PolarFire Evaluation Kit offers high-performance evaluation across a broad class of applications. This kit is ideally suited for high-speed transceiver evaluation, 10Gb Ethernet, IEEE1588, JESD204B, SyncE, SATA and more. The kit connections include a high pin count (HPC) FPGA mezzanine card (FMC), numerous SMAs, PCIe, Dual Gigabit Ethernet RJ45, SFP+ and USB. A 300K logic element (LE) PolarFire FPGA with DDR4, DDR3 and SPI-flash allow a broad class of high-performance designs to be developed.

图2. PolarFire FPGA评估板外形图

PolarFire FPGA评估板硬件特性:

300K LE PolarFire FPGA in an FCG1152 Package (MPF300TS-1FCG1152I)
HPC FMC Connector
1x SFP+ Cage
IEEE1588 PLL
SMA connectors for testing of full-duplex 12.7Gbps SERDES channel
4GB DDR4 x16 and 2GB DDR3 x16
PCI Express (x4) Edge Connector
2 x RJ45 for 10/100/1000 Ethernet using SGMII on GPIO
Dual 10/100/1000BASE-T PHY (VSC8575) for SyncE and 1588 application
SATA Interface
Power Management Unit for 1 or 1.05v PolarFire FPGA core voltage
USB to UART Interface
Embedded programming and debugging using SPI and JTAG
On-board Power Monitoring
2 x 1Gb SPI Flash Memory

图3. PolarFire FPGA评估板框图

图4. PolarFire FPGA评估板电路图(1)

图5. PolarFire FPGA评估板电路图(2)

图6. PolarFire FPGA评估板电路图(3)

图7. PolarFire FPGA评估板电路图(4)

图8. PolarFire FPGA评估板电路图(5)

图9. PolarFire FPGA评估板电路图(6)

图10. PolarFire FPGA评估板电路图(7)

图11. PolarFire FPGA评估板电路图(8)

图12. PolarFire FPGA评估板电路图(9)

图13. PolarFire FPGA评估板电路图(10)

图14. PolarFire FPGA评估板电路图(11)

图15. PolarFire FPGA评估板电路图(12)

图16. PolarFire FPGA评估板电路图(13)

图17. PolarFire FPGA评估板电路图(14)

图18. PolarFire FPGA评估板电路图(15)

图19. PolarFire FPGA评估板电路图(16)

图20. PolarFire FPGA评估板电路图(17)

图21. PolarFire FPGA评估板电路图(18)

图22. PolarFire FPGA评估板电路图(19)

图23. PolarFire FPGA评估板电路图(20)

图24. PolarFire FPGA评估板电路图(21)

图25. PolarFire FPGA评估板电路图(22)

图26. PolarFire FPGA评估板电路图(23)

图27. PolarFire FPGA评估板电路图(24)

图28. PolarFire FPGA评估板电路图(25)

图29. PolarFire FPGA评估板电路图(26)

图30. PolarFire FPGA评估板电路图(27)

图31. PolarFire FPGA评估板电路图(28)

图32. PolarFire FPGA评估板电路图(29)

图33. PolarFire FPGA评估板电路图(30)

图34. PolarFire FPGA评估板电路图(31)

图35. PolarFire FPGA评估板电路图(32)

图36. PolarFire FPGA评估板电路图(33)

图37. PolarFire FPGA评估板电路图(34)

图38. PolarFire FPGA评估板电路图(35)

图39. PolarFire FPGA评估板电路图(36)

图40. PolarFire FPGA评估板电路图(37)

图41. PolarFire FPGA评估板电路图(38)

图42. PolarFire FPGA评估板电路图(39)

图43. PolarFire FPGA评估板电路图(40)

图44. PolarFire FPGA评估板电路图(41)

图45. PolarFire FPGA评估板电路图(42)

图46. PolarFire FPGA评估板电路图(43)
详情请见:
https://www.microsemi.com/products/fpga-soc/fpga/polarfire-fpga#documentation

Microsemi_PolarFire_FPGA_Datasheet_DS0141.pdf

Microsemi_PolarFire_FPGA_Multi_Rate_Transceiver_Demo_Guide_DG0759.pdf

Microsemi_PolarFire_FPGA_Product_Overview_PO0137.pdf

 

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