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[原创] TI TPS7H3301-SP耐辐射DDR端电源解决方案

关键词:电源管理 DC/DC转换器 DDR3存储器

时间:2016-07-22 09:42:59       作者:TI       来源:中电网

TI公司的TPS7H3301-SP是内置了VTTREF缓冲器的TID和SEE耐辐射(65 MeV-cm2/mg)双数据速率(DDR) 3A电源稳压器,和DDR,DDR2.DDR3,DDR4和低功耗JEDEC标准兼容,输出电压0.5V到1.75V,3A沉和源电流,精度±20-mV,主要用在如单板计算机,固态记录仪和有效载荷处理中的DDR端应用.本文介绍了TPS7H3301-SP主要特性,功能框图,典型应用电路以及TPS7H3301-SP评估板(EVM)主要特性,框图,电路图和材料清单.

The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically design to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.

The TPS7H3301-SP supports and is compliant to DDR, DDR2, DDR3, DDR4, and associated low-power JEDEC specifications. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT during suspend to RAM (S3) power down mode.

TPS7H3301-SP主要特性:

5962R14288:
Radiation Hardness Assurance (RHA) Qualified to Total Ionizing Dose (TID) 100 krad(Si)
Single Event Latch-Up (SEL), Single Event Gate Rupture (SEGR), Single Event Burnout (SEB) Immune to LET = 65 MeV-cm2/mg
SET, SEFI, SEU Immune to 65 MeV-cm2/mg
Supports DDR, DDR2, DDR3, DDR3LP, and DDR4 Termination Applications and is Compliant to JEDEC Standards
Input Voltage: Supports a 2.5-V and 3.3-V Rail
Separate Low-Voltage Input (VLDOIN) Down to .9 V for Improved Power Efficiency(2)
3-A Sink and Source Termination Regulator Includes Droop Compensation
Enable Input and Power-Good Output for Power Supply Sequencing
VTT Termination Regulator
Output Voltage Range: 0.5 to 1.75 V
3-A Sink and Source Current
±20-mV Accuracy
Integrated Precision Voltage Divider Network With Sense Input
Remote Sensing (VOSNS)
VTTREF Buffered Reference
VDDQ/2 ±1% Accuracy
±10-mA Sink and Source Current
Undervoltage Lockout (UVLO), and Overcurrent Limit (OCL) Functionality Integrated

图1.TPS7H3301-SP功能框图

图2.TPS7H3301-SP典型应用电路图:2.5V VIN DDR3配置

TPS7H3301-SP评估板

TPS7H3301-SP source/sink Double Data Rate (DDR) termination regulator designed to support system needs for low noise applications.

Integrated solution with reduced system solution size, improved efficiency, and simple system design integration.

图3.TPS7H3301-SP评估板(EVM)外形图

TPS7H3301-SP评估板(EVM)主要特性:

• Input Voltage: Supports 2.5-V rail and 3.3-V rail
• VLDOIN, VDDQ voltage range: 0.9 V–3.5 V
• Build-in transient load switches (with both sinking and sourcing capability) to emulate the sink/sourcetransient behavior which helps to evaluate the dynamic performance. For ease of use, both load stepand transient timing can be modified by on-board resistors. Current information can also be monitoredonboard:
– DDR: 1.67 A sink/source transient load
– DDR2: 1.2 A sink/source transient load
– DDR3: 1.0 A sink/source transient load
– DDR4: 0.8 A sink/source transient load
• Jumper J22 (pins 1 and 2) for enable function
• Convenient test points for probing PGOOD, CLK_IN, and loop response testing
• 4-layer PCB with flexibility to use test socket as well as solder down IC.

TPS7H3301-SP评估板(EVM)典型应用:

• Radiation-tolerant DDR power applications
• Memory termination regulator for DDR, DDR2, DDR3, DDR4

图4.TPS7H3301-SP评估板(EVM)框图

图5.TPS7H3301-SP评估板(EVM)电路图(1)

图6.TPS7H3301-SP评估板(EVM)瞬板电路图
TPS7H3301-SP评估板(EVM)材料清单(BOM):



详情请见:
http://www.ti.com/lit/ds/symlink/tps7h3301-sp.pdf
http://www.ti.com/lit/ug/slvuak2/slvuak2.pdf
slvuak2.pdf
tps7h3301-sp.pdf

 

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