中国电子技术网

设为首页 网站地图 加入收藏

 

[原创] Atmel SMART SAM9G10 ARM MCU开发方案

关键词:ARM926EJ-S ARM MCU DSP 建筑物自动化 家庭娱乐 智能电网

时间:2015-07-01 10:14:35       作者:Atmel       来源:中电网

Atmel公司的SMART SAM9G10是集成了arm926EJ-S ARM Thumb处理器和扩展指令集以及Jazelle Java加速器的完整系统级芯片(SoC),266MHz时的性能达到293MIPS. SoC还集成了LCD控制器,支持黑白和多达16M彩色,有源和无源LCD显示器,主要用在建筑物自动化,家庭娱乐,智能电网,消防和安全系统,家庭显示单元和移动电子学以及视频.本文介绍了SMART SAM9G10主要特性,框图,ARM926EJ-S处理器特性以及评估板SAM9G10-EK2特性,电路图和PCB元件布局图.

The SAM9G10 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processorwith an extended DSP instruction set and Jazelle Java accelerator. It achieves 293 MIPSat 266 MHz.

The SAM9G10 is an optimized host processor for applications with an LCD display. Its integratedLCD controller supports BW and up to 16M color, active and passive LCD displays. TheExternal Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Staticmemories and features specific interface circuitry for CompactFlash and NAND Flash.

The SAM9G10 integrates a ROM-based Boot Loader supporting code shadowing from, forexample, external DataFlash® into external SDRAM. The software controlled Power ManagementController (PMC) keeps system power consumption to a minimum by selectivelyenabling/disabling the processor and various peripherals and adjustment of the operatingfrequency.

The SAM9G10 also benefits from the integration of a wide range of debug features includingJTAG-ICE, a dedicated UART debug channel (DBGU). This enables the development anddebug of all applications, especially those with real-time constraints.

SMART SAM9G10主要特性:

• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer
– 293 MIPS at 266 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
• Additional Embedded Memories
– 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
• LCD Controller
– Supports Passive or Active Displays
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel),Resolution up to 1280 x 860
• USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
• OHCI Compliant
• Dual On-chip Transceivers
• Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
• Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
• Fully Featured System Controller (SYSC) for Efficient System Management,including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a
Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
• Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a
Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
• Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– Schmitt Trigger on All Inputs
• Nineteen Peripheral DMA (PDC) Channels
• Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
• Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
– Compatibility with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit rate: up to 400 Kbits
– GEneral Call Supported in Slave Mode
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 217-ball LFBGA RoHS-compliant Package

SMART SAM9G10应用:

Building Automation
Comfort and Control
Fire and Security
Home Entertainment
Video
Smart Energy
In-Home Display Units
Mobile Electronics
Mobile Phones
PC Peripherals
Large I/O Devices

图1.SMART SAM9G10框图
ARM926EJ-S处理器特性:
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately foreach quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete AHB system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words)or 32-bit(Words)

评估板SAM9G10-EK2

The Atmel® SAM9G10-EK2 evaluation kit is an effective platform to evaluate microcontroller performance and to develop code for applications based on the
Atmel | SMART SAM9G10.

This guide is a description of the hardware included in the SAM9G10-EK2.Software files are available embedded into the board’s memory upon delivery.The SAM9G10-EK2 kit box contains the following items:

a SAM9G10-EK2 board
one A/B-type USB cable
one serial RS232 cable
one RJ45 crossed Ethernet cable
universal input AC/DC power supply with US and EU plug adapter

图2.评估板SAM9G10-EK2外形图

评估板SAM9G10-EK2特性:

The board is equipped with a SAM9G10 microcontroller in a 217-ball LFBGA package together with the following:
 64 Mbytes of SDRAM memory
 256 Mbytes of NAND Flash memory
 one serial DataFlash
 one USB device port interface
 two USB host port interfaces
 one DBGU serial communication port
 JTAG/ICE debug interface
 one Ethernet 100-base TX with three status LEDs
 one Wolfson WM8731 Audio DAC
 one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
 one Power LED and two general-purpose LEDs
 four user input pushbuttons
 one wakeup input pushbutton
 one reset pushbutton
 oneDataFlash SD/MMC card slot
 two expansion footprint connectors (solder side)
 one lithium coin cell battery retainer for 12 mm cell size
 dual pitch prototyping area

图3.评估板SAM9G10-EK2框图

图4.评估板SAM9G10-EK2电路图:板架构

图5.评估板SAM9G10-EK2电路图:电源和音频

图6.评估板SAM9G10-EK2电路图:SAM9G10 MCU

图7.评估板SAM9G10-EK2电路图:SDRAM和闪

图8.评估板SAM9G10-EK2电路图:以太网

图9.评估板SAM9G10-EK2电路图:LCD和用户接口

图10.评估板SAM9G10-EK2电路图:串行和I/O扩展

图11.评估板SAM9G10-EK2电路图:EBI串联电阻

图12.评估板SAM9G10-EK2 PCB布局图(顶层)

图13.评估板SAM9G10-EK2 PCB布局图(底层)
详情请见:
c6462.pdf">http://www.atmel.com/images/doc6462.pdf
http://www.atmel.com/images/atmel-11262-32-bit-arm926ej-s-embedded-microprocessor-sam9g10-ek2_userguide.pdf
doc6462.zip
atmel-11262-32-bit-arm926ej-s-embedded-microprocessor-sam9g10-ek2_userguide.pdf

 

猜你喜欢