[原创] Cypress CY27410可编程时钟发生器参考设计

Cypress公司的CY27410是标准性能的可编程时钟发生器,包括有四个单独的分数PLL,能以零ppm误差产生任何频率,每个PLL后面是四个单独的分频器,可从单个PLL产生四个不同频率,符合通信协议PCIe1.0/2.0/3.0, USB 2.0/3.0, SATA 1.0/2.0以及1/10GbE,晶振输入8 MHz 到48 MHz,输出频率高达25 MHz到700 MHz.本文介绍了CY27410主要特性,框图和PLL架构图,以及评估板CY3679 EVK主要特性,框图,电路图,材料清单,主要元件分布图.

The CY27410 is a standard-performance programmable clockgenerator with four independent fractional PLLs, whichgenerates any frequency with a zero-ppm synthesis error. EachPLL is followed by a set of four independent dividers to generatefour different frequencies from a single PLL. All four dividers aresynchronized to generate phase-aligned clock outputs withminimal skew. The PLLs also support the spread-spectrumfeature to reduce EMI. PLL 1 has VCXO functionality to achieveppm granularity of output frequency.

The CY27410 accepts a crystal clock or asingle-ended/differential reference clock. The device supportsup to 12 outputs, divided into two banks with six outputs each.
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