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[原创] Cypress PSoC 6 MCU高性能超低功耗IoT应用方案

关键词:Arm Cortex-M4F MCU 物联网(IoT)

时间:2020-01-13 11:04:22       来源:中电网

Cypress公司的PSoC 6 MCU是高性能超低功耗和安全MCU平台,组合了高性能微控制器和低功耗闪存技术,数字可编逻辑,高性能模数转换和标准通信与定时外设.PSoC 6器件包括广泛支持编程,测试,调试以及跟踪硬件和固件.PSoC 6器件的32位双核CPU子系统,具有单周期乘法器的150MHz Arm® Cortex®-M4F CPU(浮点和存储器保护单元),具有单周期乘法器和MPU的100MHz Cortex-M0+ CPU,用户可选择的核逻辑工作在1.1V或0.9V,器件有用于两个CPU核的8KB指令缓存,Cortex-M4核的工作电流为40 μA/MHz, Cortex-M0+核的工作电流为20 μA/MHz,器件有两个DMA控制器,每个有16个通路.PSoC 6集成了1MB应用闪存,32KB仿真EEPROM区域和32KB监视闪存,288KB SRAM具有电源和数据保留控制功能,低功耗1.7V-3.6V工作,有六个功耗模式,深度睡眠模式电流7 μA.主要用在物联网应用.本文介绍了PSoC® 6 MCU主要特性,框图,时钟图,电源连接图和PSoC 6 Wi-Fi BT原型开发板CY8CPROTO-062-4343W主要特性,框图,电路图和PCB设计图.

PSoC® 6 MCU is a high-performance, ultra-low-power and secure MCU platform, purpose-built for IoT applications. The PSoC 61product family, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flashtechnology, digital programmable logic, high-performance analog-to-digital and standard communication and timing peripherals.

The PSoC 6 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It doesnot require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are requiredto fully support debug.

The ModusToolbox Integrated Development Environment (IDE) provides fully integrated programming and debug support for thesedevices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. There are three debugaccess ports, one each for CM4 and CM0+, and a system port. These debug access ports can be enabled or disabled independentlybased on the user-generated security policies provisioned in the device.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about attacks due to amaliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled.

The PSoC Creator Integrated Development Environment (IDE) provides fully integrated programming and debug support forPSoC 6 devices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented inon-chip programmable blocks, the PSoC 6 family provides a very high level of security.

PSoC® 6 MCU主要特性:

32-bit Dual-Core CPU Subsystem
■ 150-MHz Arm® Cortex®-M4F CPU with single-cycle multiply(Floating Point and Memory Protection Unit)
■ 100-MHz Cortex-M0+ CPU with single-cycle multiply and MPU
■ User-selectable core logic operation at either 1.1 V or 0.9 V
■ 8-KB Instruction Caches for both CPU cores
■ Active CPU current slope with 1.1-V core operation
❐Cortex-M4: 40 μA/MHz
❐Cortex-M0+: 20 μA/MHz
■ Active CPU current slope with 0.9-V core operation
❐Cortex-M4: 22 μA/MHz
❐Cortex-M0+: 15 μA/MHz
■ Two DMA controllers with 16 channels each
Flash Memory Subsystem
■ 1-MB Application Flash, 32-KB emulated EEPROM area, and32-KB Supervisory Flash
■ 288-KB SRAM with power and data retention control
■ One-Time-Programmable (OTP) 1-Kb eFuse memory forvalidation and security
Low-Power 1.7-V to 3.6-V Operation
■ Six power modes for fine-grained power management
■ Deep Sleep mode current of 7 μA with 64-KB SRAM retention
■ On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter,<1 μA quiescent current
■ Backup domain with 64 bytes of memory and Real-Time Clock
Flexible Clocking Options
■ On-chip crystal oscillators (4 to 35 MHz, and 32 kHz)
■ Phase-locked Loop (PLL) for multiplying clock frequencies
■ 8 MHz Internal Main Oscillator (IMO) with ±2% accuracy
■ Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)
frequency Locked Loop (FLL) for multiplying IMO frequency
QSPI Interface (QSPI)/Serial Memory Interface (SMIF)
■ Execute-In-Place (XIP) from external Quad SPI Flash
■ On-the-fly encryption and decryption
■ 4-KB cache for greater XIP performance with lower power
■ Supports single, dual, quad, dual-quad, and octal interfaces w/throughput up to 640 Mbps
Serial Communication
■ Nine run-time configurable serial communication blocks(SCBs)
❐Eight SCBs: configurable as SPI, I2C, or UARTs
❐One Deep Sleep SCB: configurable as SPI or I2C
■ USB Full-Speed Dual-role Host and Device interface
Audio Subsystem
■ Two PDM channels and one I2S channel with TDM mode
Timing and Pulse-Width Modulation
■ Thirty-two timer/counter pulse-width modulators (TCPWM)
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals
Programmable Analog
■ 12-bit 1-Msps SAR ADC with differential and single-endedmodes and 16-channel sequencer with result averaging
■ Two low-power comparators available in Deep Sleep andHibernate modes
■ Built-in temp sensor connected to ADC
■ One 12-bit voltage mode DAC with < 5-μs settling time
■ Two opamps with low-power operation modesUSB Full-Speed Dual-role Host and Device interface
Up to 102 Programmable GPIOs
■ Two Smart I/O ports (16 I/Os) enable Boolean operations onGPIO pins; available during Deep Sleep
■ Programmable drive modes, strengths, and slew rates
■ Six overvoltage-tolerant (OVT) pins
Capacitive Sensing
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-classSNR, liquid tolerance, and proximity sensing
■ Enables dynamic usage of both self and mutual sensing
■ Automatic hardware tuning (SmartSense™)
Security Built into Platform Architecture
■ ROM-based root of trust via uninterruptible Secure Boot
■ Step-wise authentication of execution images
■ Secure execution of code in execute-only mode for protectedroutines
■ All Debug and Test ingress paths can be disabled
■ Up to eight Protection Contexts
Cryptography Accelerators
■ Hardware acceleration for symmetric and asymmetriccryptographic methods and hash functions
■ True Random Number Generator (TRNG) function
Programmable Digital
■ 12 programmable logic blocks, each with 8 Macrocells and an8-bit data path (called universal digital blocks or UDBs)
■ Usable as drag-and-drop Boolean primitives (gates, registers),or as Verilog programmable blocks
■ Cypress-provided peripheral component library using UDBs toimplement functions such as Communication peripherals (forexample, LIN, UART, SPI, I2C, S/PDIF and other protocols),Waveform Generators, Pseudo-Random Sequence (PRS)generation, and many other functions.)
Energy Profiler
■ Block that provides history of time spent in different powermodes
■ Allows software energy profiling to observe and optimizeenergy consumption
Packages
■ 124-BGA package
■ 80-WLCSP (in 0.33 and 0.43 mm heights)
■ Thin 80-WLCSP package (0.33 mm height) (qualification inprocess)

图1.PSoC® 6 MCU框图

图2.PSoC® 6 MCU时钟框图

图3.PSoC® 6 MCU电源连接图

PSoC 6 Wi-Fi BT原型开发板(CY8CPROTO-062-4343W)

Thank you for your interest in the CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit. ThePSoC 6 Wi-Fi BT Prototyping Kit enables you to evaluate and develop your applications using thePSoC 6 MCU and CYW4343W WICED Wi-Fi/BT combo device.

PSoC 6 MCU is Cypress’latest, ultra-low-power PSoC specifically designed for wearables and IoTproducts. PSoC 6 MCU is a true programmable embedded system-on-chip, integrating a 150-MHzArm® Cortex®-M4 as the primary application processor, a 100-MHz Arm Cortex®-M0+ that supportslow-power operations, up to 2 MB Flash and 1 MB SRAM, Secure Digital Host Controller (SDHC)supporting SD/SDIO/eMMC interfaces, CapSense® touch-sensing, and programmable analog anddigital peripherals that allow higher flexibility, in-field tuning of the design, and faster time-to-market.

You can use ModusToolbox™ to develop and debug your PSoC 6 MCU and CYW4343W applications. ModusToolbox software is a set of tools that enable you to integrate Cypress devicesinto your existing development methodology. One of the tools is a multi-platform, Eclipse-basedIntegrated Development Environment (IDE) that supports configuration and applicationdevelopment, called ModusToolbox IDE.

The PSoC 6 Wi-Fi BT Prototyping Kit has the following contents.
■ PSoC 6 Wi-Fi BT Prototyping Board
■ USB Type-A to Micro-B cable
■ Quick Start Guide (printed on the kit package)

图4.原型开发板CY8CPROTO-062-4343W元件外形图

原型开发板包含:

PSoC 6 Wi-Fi BT Prototyping Board
USB Type-A to Micro-B cable
Quick Start Guide (printed on the kit package)

图5.原型开发板CY8CPROTO-062-4343W引脚图

图6.原型开发板CY8CPROTO-062-4343W框图

图7.原型开发板CY8CPROTO-062-4343W电路图(1)

图8.原型开发板CY8CPROTO-062-4343W电路图(2)

图9.原型开发板CY8CPROTO-062-4343W电路图(3)

图10.原型开发板CY8CPROTO-062-4343W电路图(4)

图11.原型开发板CY8CPROTO-062-4343W电路图(5)

图12.原型开发板CY8CPROTO-062-4343W电路图(6)

图13.原型开发板CY8CPROTO-062-4343W PCB设计图(1)

图14.原型开发板CY8CPROTO-062-4343W PCB设计图(2)

图15.原型开发板CY8CPROTO-062-4343W PCB设计图(3)

图16.原型开发板CY8CPROTO-062-4343W PCB设计图(4)

图17.原型开发板CY8CPROTO-062-4343W PCB设计图(5)

图18.原型开发板CY8CPROTO-062-4343W PCB设计图(6)

图19.原型开发板CY8CPROTO-062-4343W PCB设计图(7)

图20.原型开发板CY8CPROTO-062-4343W PCB设计图(8)

图21.原型开发板CY8CPROTO-062-4343W PCB设计图(9)

图22.原型开发板CY8CPROTO-062-4343W PCB设计图(10)

图23.原型开发板CY8CPROTO-062-4343W PCB设计图(11)
详情请见:
https://www.cypress.com/file/498986/download
https://www.cypress.com/file/385931/download
以及https://www.cypress.com/file/457816/download
https://www.cypress.com/file/457891/download
CY8CMOD-062-4343W PCA BOM.xls
PSoC_6_MCU_CY8C62X5_Datasheet_PRELIMINARY.pdf
002-21414_PSoC_6_MCU_PSoC_61_Datasheet_Programmable_System-on-Chip_PSoC.pdf
PSoC 6 Wi-Fi BT Prototyping Kit Guide_0_0.pdf
CY8CMOD-062-4343W Module.zip

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