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[原创] MicrosemiPolarFire低功耗多核SoC FPGA开发方案

关键词:PolarFire SoC FPGA RISC-V 处理器

时间:2019-12-27 11:08:33       来源:中电网

Microsemi公司PolarFire®SoC FPGA系列产品是最低功耗多核RISC-V SoC FPGA,提供低功耗,热效率和国防级安全的无与伦比组合,用于智能的连接系统. PolarFireSoC是基于获奖的PolarFire FPGA架构,集成了多功能低功耗64位多核RISC-V 处理器,具有五Linux功能处理器子系统. RISC-V CPU微架构实现了简单5级单个议题有序流水线,不会出现通常故障机器所遇到的CPU漏洞和幽灵的问题.微处理器子系统具有64位RV64GC四个应用处理核,最大工作频率667MHz(-40°到100℃ Tj),具有3.0 CoreMarks®/MHz, 2.0 DMIPs/MHz性能,L1存储器子系统有单误差修正,双误差检测(SECDED),32KB 8路指令缓存或可选择28KB紧密的集成存储器,32KB 8路数据缓存,存储器管理单元(MMU),物理存储器保护(PMP)单元,其中的64位RV64IMAC监测处理器核,最大工作频率667MHz (-40℃ 到100℃ Tj),具有3.0 CoreMarks®/ MHz,2.0 DMIPs/MHz性能.器件中的FPGA有多达461K逻辑元件,包含4输入查找表(LUT)和可断裂D触发器,还包括20KB双端口内置了SECDED的大静态随机存储器(LSRAM)区块,64x12双端口μRAM区块,具有预加法,48位累加器和可选择的16深x16系数ROM的18x18算法区块,内置的μPROM,高速串行连接和内置多吉比特多协议收发器,速率从250 Mbps 到12.7 Gbps,广泛用于各种图像和视频应用包括监控和互联网协议(IP)摄像头,车载和其他无线与移动应用,机器视觉与医疗,智能家居以及在工业,航天与航空及国防领域等.本文介绍了PolarFire®SoC FPGA系列主要特性,包括微处理器子系统特性,FPGA特性,低功耗特性,可靠性和安全特性,框图和器件系列产品特性表,以及评估板PolarFireSoC Icicle (PN MPFS250-KIT)指标和电路图.

PolarFire™ SoC is built upon the award-winning PolarFire FPGA non-volatile FPGA platform. Featuring a fivecore Linux capable processor subsystem based on the RISC-V ISA, PolarFireSoC brings to market a royalty-free,innovative, mid-range, embedded compute platform that inherits all the benefits of the PolarFire FPGAproduct family. The RISC-V CPU micro-architecture implementation is a simple, 5-stage single issue in order
pipeline that doesn’t suffer from the Meltdown and Spectre exploits found in common out-of-order machines.

All five CPU cores are coherent with the memory subsystem allowing a versatile mix of deterministic realtime systems and Linux in a single, multi-core CPU cluster. With Secure Boot built-in, innovative Linux andReal Time modes, a large Flexible L2 memory subsystem, and a rich set of embedded peripherals, PolarFireSoC provides designers new choices in secure, power-efficient, embedded compute platforms. This document
describes the features of PolarFireSoC extended commercial (0℃ to 100℃ Tj) and industrial (–40℃ to100℃ Tj) device offerings.


• 64-bit RV64GC Quad Application processing cores, Fmax of 667 MHz (-40 ℃ to 100 ℃ Tj), 3.0CoreMarks®/MHz, 2.0 DMIPs/MHz
◦ L1 memory subsystem with single-error correct, double-error detect (SECDED)
▪ 32 KB 8-way instruction cache or optional 28 KB tightly integrated memory
▪ 32 KB 8-way data cache
▪ Memory Management Unit (MMU)
▪ Physical Memory Protection (PMP) unit
• 64-bit RV64IMAC monitor processor core, Fmax of 667 MHz (-40℃ to 100℃ Tj), 3.0 CoreMarks®/MHz,2.0 DMIPs/MHz
◦ L1 memory subsystem with SECDED
▪ 16 KB 2-way instruction cache
◦ 8 KB scratch pad memory
◦ PMP unit
• Flexible 2 MB L2 memory subsystem with SECDED configurable as:
◦ 16-way set associative L2 cache
◦ Loosely Integrated Memory (LIM) mode for deterministic access
◦ Coherent Scratchpad Memory mode for shared messages across cores
• Integrated 36-bit DDR4/DDR3/LPDDR4/LPDDR3 memory controller with SECDED
◦ DDR4 at 1.6 Gbps with a 8 GB address reach
• Cache coherent CPU bus matrix
• AMBA I/O switch with QoS and memory protection
• Integrated 128 KB embedded non-volatile memory (eNVM) for boot
• Boot options
◦ Microchip secure boot
◦ User defined, PUF-protected secure boot
◦ Boot directly from eNVM
• Platform interrupt controller
◦ 185 interrupt sources from the microprocessor subsystem and FPGA fabric with 7 priority levels
• Local interrupt controller
◦ 48 local interrupts sourced from the FPGA drive the local interrupt controller on each core
• Debug
◦ 10 hardware triggers per CPU (triggers can be configured as a breakpoint or a watchpoint)
◦ Instruction trace on all CPUs
◦ Performance counters
◦ Runtime-configurable AXI bus monitors
▪ Monitor AXI commands to DDR
▪ Monitor an AXI port going into or out of the AMBA I/O AXI switch
◦ 32-bit fabric monitor
◦ SmartDebug
▪ Dynamically monitor any 2 nets in the FPGA on 2 pins without changing the FPGA design
▪ Read/write to FPGA flip-flops and memories
▪ Halt clock trees, inspect logic tree
▪ FPGA breakpoints
▪ SmartDebug integrated into processor debug transport layer—debug from a single tool chain
◦ Secure debug remotely over Ethernet (both the processor subsystem and the FPGA design)
• Processor I/O
◦ 2 Gige MACs
◦ 1 USB 2.0 OTG
◦ 2 CAN 2.0 A and B
◦ Execute in place Quad SPI flash controller
◦ 5 multi-mode UARTs
◦ 2 SPI, 2 I2C
◦ 5 watchdog timers
◦ Timers
• Processor to FPGA Interconnect
◦ 2 64-bit AXI4 processor-to-fabric interfaces
◦ 3 64-bit AXI4 fabric-to-processor interfaces
◦ 1 32-bit APB processor-to-fabric interface
• Up to 461K logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flip-flop
• 20 KB dual- or two-port large static random access memory (LSRAM) block with built-in SECDED
• 64 × 12 two-port μRAM block implemented as an array of latches
• 18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16-deep × 18 coefficientROM
• Built-in μPROM, modifiable at program time and readable at run time for user data storage
• High-speed serial connectivity with built-in, multi-gigabit, multi-protocol transceivers from 250 Mbpsto 12.7 Gbps
• Integrated dual x4 PCIe Gen2 endpoint (EP) and root port (RP) designs
• High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 MbpsLPDDR3/DDR3 memories with integrated I/O digital
• General-purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps DDR3,and 1250 Mbps LVDS I/O speed with integrated I/O digital logic
• Low-power, phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low jitter
• 1.0 V and 1.05 V operating modes
• Low device static power
• Low inrush current
• Low-power transceivers
• FPGA configuration cells single-event upset (SEU) immune
• Built-in SECDED and memory interleaving on FPGA fabric LSRAMs
• SECDED on all processor memories
◦ Error signals trapped and exported to the FPGA fabric
• System controller suspend mode for safety-critical designs
• Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bitstreamprotection
• Integrated dual physically unclonable function (PUF)
• 56 KB of secure, non-volatile memory (sNVM)
• Built-in tamper detectors and countermeasures
• Digest integrity check for FPGA, μPROM, sNVM, and eNVM

图1.PolarFireSoC FPGA框图
PolarFireSoC FPGA特性表:

PolarFireSoC FPGA板设计指南

The PolarFireSoC family offers the industry’s first RISC-V based SoC FPGAs. The PolarFireSoC familycombines a powerful 64-bit 5x core RISC-V Microprocessor Sub-System (MSS) with the FPGA fabric in asingle device. Packed with this powerful combination, PolarFireSoC devices offer the scalable featuresof FPGAs and high-performance of ASICs like DDR3/DDR4, 12.7G Transceiver, PCIe Gen2 andHSIO/GPIO and a highly configurable MSS subsystem.

图2.PolarFireSoC FPGA电源图

The PolarFireSoC family offers the industry’s first RISC-V based SoC FPGAs. The PolarFireSoC familycombines a powerful 64-bit 5x core RISC-V Processor Sub-System (MSS) with the FPGA fabric in asingle device. Packed with this powerful combination, PolarFireSoC devices offer the scalable featuresof FPGAs and high-performance of ASICs. Only the FPGA fabric resources vary and the MSS remainsthe same across PolarFireSoC device variants, making these devices ideal for many applications.

PolarFireSoC FPGAs are ideal for running full-fledged Operating Systems (Linux) using the 5x coreMSS, which includes four 64-bit RISC-V application cores and a 64-bit RISC-V monitor core.

图3.PolarFireSoC MSS(处理器子系统)高档框图
PolarFireSoC MSS主要特性:

图4.PolarFireSoC MSS(处理器子系统)详细框图

评估板PolarFireSoC Icicle套件(PN MPFS250-KIT)

What’s not new is the development platform for MicroSemiPolarFireSoCs, and it combines RISC-V based HiFive Unleashed Linux development board together with the FPGA Expansion Board introduced last May.


评估板PolarFireSoC Icicle(PN MPFS250-KIT)指标:

SoC FPGA – PolarFireSoC MPFS250T-1FCVG484 penta–core RISC-V CPU subsystem (1xRV64IMAC, 4xRV64GC) with 254k LE non-volatile fabric, 784 18 × 18 math blocks, secure boot, 4× 12.7 Gbps SERDES, FCVG484 package(19 × 19 mm, 0.8 mm pitch)
System Memory – LPDDR4 x32
Storage – QSPI Flash, eMMC Flash
Video Output – HDMI 2.0
Connectivity – 2x Gigabit Ethernet, Wi-Fi, and Bluetooth
USB – micro USB 2.0 OTG port, micro USB port for debugging
Expansion Ports
40-pin Raspberry Pi compatible header with GPIO, I2C, SPI, UART,
PCIe connector, USB 2.0, UART, SPI, I2C, CAN, HDMI 2.0
Sensor – Power sensor
Debugging – JTAG + micro USB (UART)
Misc – 4x LEDs, 4x buttons

图5.评估板PolarFireSoC Icicle电路图(1)

图6.评估板PolarFireSoC Icicle电路图(2)

图7.评估板PolarFireSoC Icicle电路图(3)

图8.评估板PolarFireSoC Icicle电路图(4)

图9.评估板PolarFireSoC Icicle电路图(5)

图10.评估板PolarFireSoC Icicle电路图(6)

图11.评估板PolarFireSoC Icicle电路图(7)

图12.评估板PolarFireSoC Icicle电路图(8)

图13.评估板PolarFireSoC Icicle电路图(9)

图14.评估板PolarFireSoC Icicle电路图(10)

图15.评估板PolarFireSoC Icicle电路图(11)

图16.评估板PolarFireSoC Icicle电路图(12)

图17.评估板PolarFireSoC Icicle电路图(13)

图18.评估板PolarFireSoC Icicle电路图(14)

图19.评估板PolarFireSoC Icicle电路图(15)

图20.评估板PolarFireSoC Icicle电路图(16)

图21.评估板PolarFireSoC Icicle电路图(17)

图22.评估板PolarFireSoC Icicle电路图(18)

图23.评估板PolarFireSoC Icicle电路图(19)

图24.评估板PolarFireSoC Icicle电路图(20)

图25.评估板PolarFireSoC Icicle电路图(21)

图26.评估板PolarFireSoC Icicle电路图(22)

图27.评估板PolarFireSoC Icicle电路图(23)

图28.评估板PolarFireSoC Icicle电路图(24)

图29.评估板PolarFireSoC Icicle电路图(25)

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