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[原创] Microsemi PolarFire FPGA系列开发方案

关键词:PolarFire FPGA 物联网(IoT) 工业自动化 通信设备 有线接入网

时间:2017-07-05 11:21:46       作者:Microsemi       来源:中电网

Microsemi公司的PolarFire FPGA系列具有最低功耗最佳成本的中等规模的FPGA,逻辑单元(LE)从100K到500K,12.7G 收发器, 1.6 Gbps I/O,比同类产品的功耗低50%以上.主要用在物联网(IoT),工业自动化,通信设备,有线接入网,蜂窝基础设备,国防和航空通信领域.本文介绍了PolarFire FPGA系列主要特性,低功耗特性,可靠性和安全特性,框图,以及评估板MPF300-EVAL-KIT-ES主要特性,框图和电路图.

PolarFire™ FPGAs are the fifth-generation family of non-volatile FPGA devices from Microsemi, built on state-of-the-art 28nm non-volatile process technology. Cost-optimized PolarFire FPGAs deliver the lowest power at mid-range densities. PolarFire FPGAs lower the cost of mid-range FPGAs by integrating the industry’s lowest power FPGA fabric, lowest power 12.7 Gbps transceiver lane, built-in low power dual PCI Express Gen2 (EP/RP), and, on select data security (S) devices, an integrated low-power crypto co-processor. PolarFire FPGAs can operate at 1.0 V and 1.05 V, offering the end user the ability to trade off power and performance to match the application requirements.

Microsemi's lowest power, cost-optimized mid-range PolarFire FPGA engineering samples are now available for all customers. The PolarFire FPGA family spans from 100K logic elements (LEs) to 500K LEs, features 12.7G transceivers, and offers up to 50% lower power than competing mid-range FPGAs. The devices are ideal for a wide range of applications within wireline access networks and cellular infrastructure, defense and commercial aviation markets, as well as industrial automation and IoT markets.

Cost-optimized Architecture

Architecture and process optimizations for 100K/500K LE devices

Transceiver performance optimized for 12.7 Gbps, which yields smaller size

1.6 Gbps I/Os—hardened I/O gearing logic with CDR (supports SGMII/GbE links on these GPIOs)

Best-in-class high-performance, hardened security IP in mid-range devices

Power Optimization

The lowest static power—1/10 static power vs. competing devices 

Transceiver optimized for 12.7 Gbps, which yields 1/2 the power vs. competing devices

Low power Flash*Freeze mode yields best-in-class standby power

Integrated hard IP—DDR PHY, PCIe endpoint/root port, crypto processor

Total power (static and dynamic)—up to 50% lower power

PolarFire FPGAs deliver up to 500K logic elements, 12.7G transceivers at 50% lower power.

PolarFire FPGA系列主要特性:

Up to 481K logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flipflop

20 Kb dual- or two-port large static random access memory (LSRAM) block with a built-in single error

correct double error detect (SECDED)

64 × 12 two-port μRAM block implemented as an array of latches

18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16 deep x 18 coefficient ROM

Built-in μPROM, modifiable at program time, readable at run time for user data storage

High-speed serial connectivity with built-in multi-gigabit multi-protocol transceivers from 250 Mbps

to 12.7 Gbps

Integrated dual PCIe for up to ×4 Gen2 endpoint (EP) and root port (RP) designs

High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps

LPDDR3/DDR3 memories with integrated I/O digital

General purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps

DDR3, and 1600 Mbps LVDS I/O speed with integrated I/O digital logic

Low-power phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low-jitter

1.0 V and 1.05 V operating modes

PolarFire FPGA系列低功耗特性:

Low device static power

Low inrush current

Low power transceivers

Unique Flash*Freeze (F*F) mode

PolarFire FPGA系列可靠性特性:

FPGA configuration cells single event upset (SEU) immune

Built-in SECDED and memory interleaving on LSRAMs

System controller suspend mode for safety-critical designs

PolarFire FPGA系列安全特性:

Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bitstream

protection

Integrated physically unclonable function (PUF)

56 KBytes of secure non-volatile memory (sNVM)

Built-in tamper detectors and countermeasures

Digest integrity check for FPGA, μPROM, and sNVM

Data security features in S devices—true random number generator, integrated Athena TeraFire

EXP5200B Crypto Coprocessor, suite B capable, and CRI DPA countermeasure pass-through license

图1. PolarFire FPGA框图

PolarFire FPGA评估板MPF300-EVAL-KIT-ES

Microsemi’s PolarFire Evaluation Kit is an ideal platform for evaluating the lowest power, cost-optimized, non-volatile PolarFire FPGAs. This kit has a full-featured 300K LE PolarFire FPGA, which integrates reliable non-volatile FPGA fabric, 12.7 Gbps transceivers, 1.6 Gbps I/Os, best-in-class-performance, hardened security IP, and crypto processors. The silicon features power optimization with the lowest static power for 28 nm non-volatile FPGAs, its low power mode; Flash*Freeze yields best-in-class standby power and it has integrated DDR PHY, PCIe endpoint/root port, crypto processor hard IPs.

评估板MPF300-EVAL-KIT-ES主要特性:

300K LE PolarFire FPGA in an FCG1152 package (MPF300TS-1FCG1152I)

HPC FMC connector

1x SFP+ cage

IEEE1588 phase-locked loop (PLL)

SMA connectors for testing of full-duplex 12.7Gbps SerDes channel

4GB DDR4 x32 and 2GB DDR3 x16

PCI Express (x4) edge connector

2 x RJ45 for 10/100/1000 Ethernet using serial gigabit media-independent interface (SGMII) on general purpose input/output (GPIO)

Dual 10/100/1,000 BASE-T PHY (VSC8575) for SyncE and 1588 application

Power management unit for 1 or 1.05 volt (V) PolarFire FPGA core voltage

USB to universal asynchronous receiver/transmitter (UART) interface

Embedded programming and debugging using serial peripheral interface (SPI) and Joint Test Action Group (JTAG)

On-board power monitoring

2 x 1Gb SPI flash memory

图2. 评估板MPF300-EVAL-KIT-ES外形图

图3. 评估板MPF300-EVAL-KIT-ES框图

图4. 评估板MPF300-EVAL-KIT-ES电路图(1)

图5. 评估板MPF300-EVAL-KIT-ES电路图(2)

图6. 评估板MPF300-EVAL-KIT-ES电路图(3)


图7. 评估板MPF300-EVAL-KIT-ES电路图(4)

图8. 评估板MPF300-EVAL-KIT-ES电路图(5)

图9. 评估板MPF300-EVAL-KIT-ES电路图(6)

图10. 评估板MPF300-EVAL-KIT-ES电路图(7)

图11. 评估板MPF300-EVAL-KIT-ES电路图(8)

图12. 评估板MPF300-EVAL-KIT-ES电路图(9)

图13. 评估板MPF300-EVAL-KIT-ES电路图(10)

图14. 评估板MPF300-EVAL-KIT-ES电路图(11)

图15. 评估板MPF300-EVAL-KIT-ES电路图(12)

图16. 评估板MPF300-EVAL-KIT-ES电路图(13)

图17. 评估板MPF300-EVAL-KIT-ES电路图(14)

图18. 评估板MPF300-EVAL-KIT-ES电路图(15)

图19. 评估板MPF300-EVAL-KIT-ES电路图(16)

图20. 评估板MPF300-EVAL-KIT-ES电路图(17)

图21. 评估板MPF300-EVAL-KIT-ES电路图(18)

图22. 评估板MPF300-EVAL-KIT-ES电路图(19)

图23. 评估板MPF300-EVAL-KIT-ES电路图(20)

图24. 评估板MPF300-EVAL-KIT-ES电路图(21)

图25. 评估板MPF300-EVAL-KIT-ES电路图(22)

图26. 评估板MPF300-EVAL-KIT-ES电路图(23)

图27. 评估板MPF300-EVAL-KIT-ES电路图(24)

图28. 评估板MPF300-EVAL-KIT-ES电路图(25)

图29. 评估板MPF300-EVAL-KIT-ES电路图(26)

图30. 评估板MPF300-EVAL-KIT-ES电路图(27)

图31. 评估板MPF300-EVAL-KIT-ES电路图(28)

图32. 评估板MPF300-EVAL-KIT-ES电路图(29)

图33. 评估板MPF300-EVAL-KIT-ES电路图(30)

图34. 评估板MPF300-EVAL-KIT-ES电路图(31)

图35. 评估板MPF300-EVAL-KIT-ES电路图(32)

图36. 评估板MPF300-EVAL-KIT-ES电路图(33)

图37. 评估板MPF300-EVAL-KIT-ES电路图(34)

图38. 评估板MPF300-EVAL-KIT-ES电路图(35)

图39. 评估板MPF300-EVAL-KIT-ES电路图(36)

图40. 评估板MPF300-EVAL-KIT-ES电路图(37)

图41. 评估板MPF300-EVAL-KIT-ES电路图(38)

图42. 评估板MPF300-EVAL-KIT-ES电路图(39)

图43. 评估板MPF300-EVAL-KIT-ES电路图(40)

图44. 评估板MPF300-EVAL-KIT-ES电路图(41)

图45. 评估板MPF300-EVAL-KIT-ES电路图(42)

图46. 评估板MPF300-EVAL-KIT-ES电路图(43)
详情请见:
https://www.microsemi.com/products/fpga-soc/fpga/polarfire-fpgaMicrosemi_PolarFire_Evaluation_Kit_Quickstart_Card.pdf
Microsemi_PolarFire_FPGA_Datasheet_DS0141.pdfMicrosemi_PolarFire_FPGA_Evaluation_Kit_User_Guide_UG0747_V1.pdfMicrosemi_PolarFire_FPGA_Product_Overview_PO0137.pdf

 

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