中国电子技术网

设为首页 网站地图 加入收藏

 

[原创] Linear LTC2500-32 32位过取样ADC解决方案

关键词:工业仪表 自动测试(ATE) LTC2500-32

时间:2017-06-12 13:10:42       作者:Linear       来源:中电网

Linear公司的LTC2500-32是带可配置数字滤波器的 32位过取样ADC,具有低噪音低功耗和高性能等特性,工作电压2.5V,差分全输入范围±VREF,而VREF从2.5V到5.1V.器件具有±0.5ppm INL (典型),1Msps时的SNR为104dB,61sps时的动态范围148dB,保证32位不丢失码.主要用在地震学,能源勘探,自动测试(ATE)和高精度仪表.本文介绍了LTC2500-32主要特性,框图,应用电路图和演示板DC2390A主要特性,电路图,材料清单和PCB装配文件图.

The LTCR2500-32 is a low noise, low power, high performance32-bit ADC with an integrated configurable digitalfilter. Operating from a single 2.5V supply, the LTC2500-32 features a fully differential input range up to ±VREF,withVREF ranging from 2.5V to 5.1V. The LTC2500-32 supportsa wide common mode range from 0V to VREF simplifyinganalog signal conditioning requirements.

The LTC2500-32 simultaneously provides two outputcodes: (1) a 32-bit digitally filtered high precision lownoise code, and (2) a 32-bit no latency composite code.

The configurable digital filter reduces measurement noiseby lowpass filtering and down-sampling the stream of datafrom the SAR ADC core, giving the 32-bit filtered output code. The 32-bit composite code consists of an overrangedetection bit, a 24-bit code representing the differentialinput voltage and a 7-bit code representing the commonmode input voltage. The 32-bit composite code is availableeach conversion cycle, with no cycle of latency.

The digital filter is highly configurable through the SPIcompatibleinterface and features many distinct filter typesthat suit a variety of applications. The digital lowpass filterrelaxes the requirements for analog anti-aliasing. MultipleLTC2500-32 devices can be easily synchronized usingthe SYNC pin.

LTC2500-32主要特性:

±0.5ppm INL (Typ)
104dB SNR (Typ) at 1Msps
148dB Dynamic Range (Typ) at 61sps
Guaranteed 32-Bits No Missing Codes
Configurable Digital Filter with Synchronization
Relaxed Anti-Aliasing Filter Requirements
Dual Output 32-Bit SAR ADC
32-Bit Digitally Filtered Low Noise Output
24-Bit Differential + 7-Bit Common Mode 1MspsOutput with Overrange Detection
Wide Input Common-Mode Range
Guaranteed Operation to 85℃
1.8V to 5V SPI-Compatible Serial I/O
Low Power: 24mW at 1Msps
24-Lead 7mm × 4mm DFN Packages

LTC2500-32应用:

Seismology
Energy Exploration
Automatic Test Equipment
High Accuracy Instrumentation

图1.LTC2500-32框图

图2.LTC2500-32典型应用电路图

图3.LTC2500-32应用电路图:缓冲和转换+/-10V双极输入信号成全差分ADC输入

演示板DC2390A

Demonstration circuit 2390A is a general-purpose testplatform for prototyping and evaluating some of thekey applications for the LTC2500 family of high resolution,oversampling ADCs. Assembly type A includes twoLTC®2500-32, 32-bit oversampling ADCs with configurabledigital filters, two LTC1668 16-bit, 50Msps DACs,analog signal conditioning, and clock generation. (Otherdash options are reserved for future use). All power forbasic experiments is taken from the host FPGA board.

The digital interface is an HSMC (high speed mezzanineconnector), which is compatible with the Altera Cyclone5 SoCkit and other Altera FPGA evaluation boards thatsupport 3.3V CMOS I/O.

This demo manual covers the basic functionality of DC2390.Additional experiments and applications are documentedelsewhere.

图4.演示板DC2390A外形图

图5.演示板DC2390A框图

图6.演示板DC2390A电路图(1)

图7.演示板DC2390A电路图(3)

图8.演示板DC2390A电路图(3)

图9.演示板DC2390A电路图(4)

图10.演示板DC2390A电路图(5)

图11.演示板DC2390A电路图(6)

图12.演示板DC2390A PCB装配图(1)

图13.演示板DC2390A PCB装配图(2)
演示板DC2390A材料清单见:
DC2390A-4-BOM.XLS
详情请见:
http://cds.linear.com/docs/en/datasheet/250032f.pdf
http://cds.linear.com/docs/en/demo-board-manual/DC2390AF.PDF
以及http://cds.linear.com/docs/en/demo-board-schematic/DC2390A4-SCH.PDF
250032f.pdf
DC2390AF.PDF
DC2390A.zip
DC2390A4-SCH.PDF

 

猜你喜欢